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1 datasheet 2-phase boost controller with drivers and i 2 c/pmbus? isl78229 the isl78229 is an automotive grade (aec-q100 grade 1), 2-phase 55v synchronous boost co ntroller intended to simplify the design of high power boos t applications. it integrates strong half-bridge drivers, an analog/digital tracking input, comprehensive protection functions and a pmbus? interface for added control and telemetry. isl78229 enables a simple, modular design for systems requiring power and thermal scalab ility. it offers peak-current mode control for fast line resp onse and simple compensation. its synchronous 2-phase architecture enables it to support higher current while reducing the size of input and output capacitors. the integrated drivers feature programmable adaptive dead time control offe ring flexibility in power stage design. isl78229 offers a 90output clock and supports 1-, 2- and 4-phases. isl78229 offers a highly robu st solution for the most demanding environments. its unique soft-start control prevents large negative current even in extreme cases, such as a restart under high output prebias on high volume capacitances. it also offers two levels of cycle-by-cycle overcurrent protection, average current limiting, input ovp, output uvp/ovp and internal otp. a thermistor input is provided for external otp for the power-stage elements. in the event of a fault, the isl78229 offers individually programmable latch-off or hiccup recovery for each fault type. also integrated are several func tions that ease system design. a unique tracking input is availa ble that can control the output voltage, allowing it to track either a digital duty cycle (pwm) signal or an analog refere nce. isl78229 provides input average current limiting so the system can deliver transient bursts of high load current while limiting the average current to avoid overheating. finally, the isl78229 pmbus? interface provides fault reporting, telemetry and system control to support functional safety qualification. features ? input/output voltage range: 5v to 55v, withstands 60v transients ? supports synchronous or standard boost topology ? peak current mode control with adjustable slope compensation ? secondary average current control loop ? integrated 5v 2a sourcing/3 a sinking n-channel mosfet drivers ? switching frequency: 50khz to 1.1mhz per phase ? external synchronization ? programmable minimum duty cycle ? programmable adaptive dead time control ? optional diode emulation and phase dropping ? pwm and analog track function ? forced pwm operation with negative current limiting and protection ? comprehensive protection/fault reporting ? selectable hiccup or latch-off fault response ?i 2 c/pmbus? compatible digital interface ? aec-q100 qualified, grade 1: -40c to +125c ? 6mmx6mm 40 ld wfqfn (wettable flank qfn) package applications ? automotive power system (e.g., 12v to 24v, 12v to 48v, etc.) - trunk audio amplifier - start-stop system - automotive boost applications ? industrial and telecommunication power supplies figure 1. simplified application schematic, 2-phase synchronous boost figure 2. efficiency curves, v in = 12v, t a = +25c isl78229 boot1 ph1 ntc fb vout lg1 clkout pgood ug1 boot2 ph2 lg2 ug2 ss vin en track sda scl salert pmbus en_ic isen1n isen1p isen2n isen2p comp r sen1 r sen2 power-good clock_out pvcc vin vin 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 load current (a) v o = 18v v o = 36v v o = 24v efficiency (%) note: (see typical application in figure 4 on page 8 .) february 12, 2016 fn8656.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl78229 2 fn8656.3 february 12, 2016 submit document feedback table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical application - 2-phase synchronous boost . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 recommended operating conditions . . . . . . . . . . . . . . . . . . 9 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 operation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 synchronous boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 multiphase power conversion . . . . . . . . . . . . . . . . . . . . . . . . . 27 oscillator and synchronization. . . . . . . . . . . . . . . . . . . . . . . . . 29 operation initialization and soft-start. . . . . . . . . . . . . . . . . . . 30 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pgood signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 current sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 adjustable slope compensation . . . . . . . . . . . . . . . . . . . . . . . 33 light-load efficiency enhancement . . . . . . . . . . . . . . . . . . . . 33 fault protections/indications. . . . . . . . . . . . . . . . . . . . . . . . . . 34 internal 5.2v ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 pmbus? user guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 monitor operating parameters via pmbus? . . . . . . . . . . . . . 40 monitor faults and configure fault responses . . . . . . . . . . . 40 set operation/fault thresholds via pmbus? . . . . . . . . . . . . 40 accessible timing for p mbus? registers status . . . . . . . . . 40 device identification address and read/write . . . . . . . . . . . 42 pmbus? data formats used in isl78229. . . . . . . . . . . . . . . 42 pmbus? command summary . . . . . . . . . . . . . . . . . . . . . . . .43 pmbus? command detail . . . . . . . . . . . . . . . . . . . . . . . . . . .46 operation (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 clear_faults (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 write_protect (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 capability (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 vout_command (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 vout_transition_rate (27h) . . . . . . . . . . . . . . . . . . . . . . . . 49 ot_ntc_fault_limit (4fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ot_ntc_warn_limit (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 read_vin (88h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 read_vout (89h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 read_iin (8ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 read_temperature (8dh) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 pmbus_revision (98h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ic_device_id (adh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ic_device_rev (aeh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 fault_status (d0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 fault_mask (d1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 set_fault_response (d2h) . . . . . . . . . . . . . . . . . . . . . . . . . 60 vout_ov_fault_limit (d3h) . . . . . . . . . . . . . . . . . . . . . . . . . 61 vout_uv_fault_limit (d4h) . . . . . . . . . . . . . . . . . . . . . . . . . 62 cc_limit (d5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 oc_avg_fault_limit (d6h) . . . . . . . . . . . . . . . . . . . . . . . . . . 64 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 output voltage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 input inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 output capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 power mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . 66 vcc input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 current sense circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 about intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
isl78229 3 fn8656.3 february 12, 2016 submit document feedback pin configuration isl78229 (40 ld 6x6 wfqfn) top view 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 vcc rdt atrk/dtrk hic/latch nc isen2p isen2n isen1p isen1n vin boot1 ug1 ph1 lg1 pvcc pgnd lg2 ph2 ug2 boot2 slope fb comp ss imon track addr1 addr2 pgood fsync sgnd sda scl salert ntc de/phdrp rblank pllcomp en clkout pad functional pin description pin name pin # description slope 1 this pin programs the slope of the internal slope compen sation. a resistor should be connected from the slope pin to gnd. refer to ? adjustable slope compensation ? on page 33 for how to select this resistor value. fb 2 the inverting input of the error amplifier for the voltage re gulation loop. a resistor network must be placed between the fb pin and the output rail to set the boost converter?s output voltage. refer to ? output voltage setting ? on page 65 for more details. there are also output overvoltage and underv oltage comparators on this pin. refer to ? output undervoltage fault ? on page 35 and ? output overvoltage fault ? on page 36 and for more details. comp 3 the output of the transconductance error amplifier (gm1) for the output voltage regulation loop. place the compensation network between the comp pin and ground. refer to ? output voltage regulation loop ? on page 26 for more details. the comp pin voltage can also be controlled by the constant current control loop error amplifier (gm2) output through a diode ( d cc ) when the constant current control loop is used to control the input average current. refer to ? constant current control (cc) ? on page 37 for more details. ss 4 a capacitor placed from ss to ground will set up the soft-sta rt ramp rate and in turn determine the soft-start time. refer to ? soft-start ? on page 31 for more details.
isl78229 4 fn8656.3 february 12, 2016 submit document feedback imon 5 imon is the average current monitor pin for the sum of the two phases? inductor cu rrents. it is used for average current l imiting and average current protection functions. the sourcing current from the imon pin is the sum of the two csa?s outputs plus a fixed 17a offset current. with each csa sensing individual phase?s inductor current, the imon signal represents the sum of th e two phases? inductor currents and it is the input current for the boost. a resistor in parallel with a capacitor are needed to be placed from imon to ground. the imon pin output current signal builds up the average voltage signal representing the average current sense signals. a constant average current limiting function and an average current protection are implemented based on the imon signal. 1. constant average current limiting: a constant current (c c) control loop is implemented to limit the imon average current signal using a 1.6v reference, which ultimately li mits the total input average current to a constant level. 2. average current protection: if the imon pi n voltage is higher than 2v, the part will go into either hiccup or latch-off fault protection as described in ? fault response register set_fault_response (d2h) ? on page 35 . refer to ? average current sense for 2 phases - imon ? on page 32 for more details. track 6 external reference input pin for the ic output voltage regu lation loop to follow. the inpu t reference signal can be eithe r digital or analog signal selected by the atrk/dtrk pin configuration. if the track function is not used, connec t the track pin to vcc and the internal vref_dac will work as the reference. refer to ? digital/analog track function ? on page 26 for more details. addr1 7 addr1, a logic input in combination with addr 2, selects one of four bus addresses. refer to ? device identification address and read/write ? on page 42 for more details. addr2 8 addr2, a logic input in combination with addr 1, selects one of four bus addresses. refer to ? device identification address and read/write ? on page 42 for more details. pgood 9 provides an open-drain power-good signal. pull up this pin with a resistor to this ic?s vcc for proper function. when the output voltage is within ov/uv threshol ds and soft-start is completed, the internal pgood open-drain transistor is open and pgood is pulled high. it will be pulled low once output uv /ov or input ov conditions are detected. refer to ? pgood signal ? on page 31 for more details. fsync 10 a dual-function pin for switching frequenc y setting and synchronization defined as follows: 1. the pwm switching frequency can be programmed by a resistor r fsync from this pin to ground. the pwm frequency refers to a single-phase switching frequency in this da tasheet. the typical programmable frequency range is 50khz to 1.1mhz. 2. the pwm switching frequency can also be synchronized to an external clock applied on the fsync pin. the fsync pin detects the input clock signal?s rising edge to be synchronized with. the typical detectable minimum pulse width of the input clock is 20ns. the rising edge of lg1 is dela yed by 35ns from the rising edge of the input clock signal at the fsync pin. once the internal clock is locked to the external clock, it will latch to the external clock. if the external clock on the fsync pin is removed, the switching frequency oscillator will shut down. the part will then detect pll_lock fault and go to either hiccup mode or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 . if the part is set in hiccup mode, th e part will restart with the frequency set by r fsync . sgnd 11 signal ground pin that the internal sensitive analog circuits refer to. connect this pin to large copper ground plane fre e from large noisy signals. in layout power flow planning, avoid having the noisy high frequency pulse current flowing through the ground area around the ic. sda 12 serial bus data input/ output. requires pull-up. scl 13 serial bus clock input. requires pull-up. salert 14 pmbus? alert output. an open-drain output that is pulle d low when a fault condition is detected. requires pull-up. refe r to ? fault flag register fault_status (d0h) and salert signal ? on page 34 for more details. ntc 15 external temperature sensor input. an ntc resistor from this pin to gnd can be used as the external temperature sensing component. a 20a current sources out of this pin. the vo ltage at this pin is 20a times the ntc resistor, which represents the temperature. the voltage on this pin is converted by the internal adc and stored in the ntc register which can be read over the pmbus?. refer to ? external temperature monitoring and protection (ntc pin) ? on page 38 for more details. de/phdrp 16 this pin is used to select diode emulation mode (de) , phase dropping (ph_drop) mode or continuous conduction mode (ccm). there are 3 configurable modes: 1. de mode; 2. de plus ph_drop mode; 3. ccm mode. refer to table 2 on page 34 for the 3 configurable options. the phase dropping mode is not allowed with external synchronization. rblank 17 a resistor from this pin to ground programs the blanking time for current sensing after the pwm is on (lg is on). this blanking time is also termed as t minon time meaning minimum on-time once a pwm pulse is on. refer to ? minimum on-time (blank time) consideration ? on page 29 for the selection of r blank . functional pin description (continued) pin name pin # description
isl78229 5 fn8656.3 february 12, 2016 submit document feedback pllcomp 18 this pin serves as the compensation node for the swit ching frequency clock?s pll (phase lock loop). a second order passive loop filter connected between this pin and ground compensates the pll loop. refer to ? oscillator and synchronization ? on page 29 for more details. en 19 this pin is a threshold-sensitive enable input for the cont roller. when the en pin is dr iven above 1.2v, the isl78229 is enabled and the internal ldo is activated to power up pvcc followed by a start-up procedure. driving the en pin below 0.95v will disable the ic and clear all fault states. refer to ? enable ? on page 31 for more details. clkout 20 this pin outputs a clock signal with same frequency to on e phase?s switching frequency. the rising edge signal on the c lkout pin is delayed by 90 from the rising edge of lg1 of the same ic. with clkout connected to the fsync pin of the second isl78229, a 4-phase interleaving operation can be achieved. refer to ? oscillator and synchronization ? on page 29 for more details. boot2 21 this pin provides bias voltage to the phase 2 high-side mo sfet driver. a bootstrap circuit is used to create a voltage s uitable to drive the external n-channel mosfet. a 0.47f ceramic capacitor in series with a 1.5 resistor are recommended between the boot2 and ph2 pins. in the typical configuration, pvcc is providing the bias to boot2 through a fast switching diode. in applications where a high-side driver is not needed (standard boost application for example), boot2 is recommended to be connected to ground. the isl78229 ic can detect boot2 being grounded during start-up and both the phase 1 and phase 2 high-side drivers will be disabled. in additi on, ph1 and ph2 should al so be tied to ground. ug2 22 phase 2 high-side gate driver output. this output can be disabled by tying either boot1 and ph1 to ground or boot2 and ph2 to ground. ph2 23 connect this pin to the source of the phase 2 high-side mosfets and the dr ain of the low-side mosfets. this pin represents the return path for the phase 2 high-side gate drive. lg2 24 phase 2 low-side gate driver output. it should be connected to the phase 2 low-side mosfets? gates. pgnd 25 provides the return path for the low-side mosfet driv ers. this pin carries a noisy driving current and the traces connecting from this pin to the low-side mosfet source and pvcc decoupling capacitor ground pad should be as short as possible. all the sensitive analog sign al traces should not share common traces with this driver return path. connect this pin to the ground copper plane (wiring away from the ic instead of connecting through the ic bottom pad) through several vias as close as possible to the ic. pvcc 26 output of the internal linear regulato r that provides bias for the low-side driver, high-side driver (pvcc connected to b ootx through diodes) and vcc bias (pvcc and vcc are ty pically connected through a small resistor like 10 or smaller, which helps to filter out the noises from pvcc to vcc). the pvcc operating range is 4.75v to 5.5v. a minimum 10f decoupling ceramic capacitor should be used between pvcc and pgnd. refer to ? internal 5.2v ldo ? on page 39 for more details. lg1 27 phase 1 low-side gate driver output. it should be connected to the phase 1 low-side mosfets? gates. ph1 28 connect this pin to the source of the phase 1 high-side mosfets and the dr ain of the low-side mosfets. this pin represents the return path for the phase 1 high-side gate drive. ug1 29 phase 1 high-side mosfet gate drive output. this output can be disabled by tying either boot1 and ph1 to ground or boot2 and ph2 to ground. boot1 30 this pin provides bias voltage to the phase 1 high-side mo sfet driver. a bootstrap circuit is used to create a voltage s uitable to drive the external n-channel mosfet. a 0.47f ceramic capacitor in series with a 1.5 resistor are recommended between boot1 and ph1 pins. in typical configura tion, pvcc is providing the bias to boot1 through a fast switching diode. in applications where a high-side driver is not needed (for example, standard boost application), the boot1 is recommended to be connected to ground. the isl78229 ic can detect boot1 being grounded during start-up and both the phase 1 and phase 2 high-side drivers will be disabled. in addition, ph1 and ph2 should also be tied to ground. vin 31 connect supply rail to this pin. typically, connect boost inpu t voltage to this pin. this pi n is connected to the input of the internal linear regulator, generating the power necessary to operate the chip. the dc voltage applied to the vin should not exceed 55v during normal operation. vin can withstand transients up to 60v, but in this case, the device's overvoltage protection will sto p it from switching to pr otect itself. refer to ? input overvoltage fault ? on page 35 for more details. isen1n 32 the isen1n pin is the negative potential input to the ph ase 1 current sense amplifier. this amplifier continuously sens es the phase 1 inductor current through a powe r current sense resistor in series with the inductor. the sensed current signal is used for current mode control, peak current li miting, average current limiting and diode emulation. isen1p 33 the isen1p pin is the positive potentia l input to the phase 1 current sense amplifier. isen2n 34 the isen2n pin is the negative potential input to the ph ase 2 current sense amplifier. this amplifier continuously sens es the phase 2 inductor current through a powe r current sense resistor in series with the inductor. the sensed current signal is used for current mode control, peak current li miting, average current limiting and diode emulation. isen2p 35 the isen2p pin is the positive phase input to the phase 2 current sense amplifier. nc 36 not connected - this pin is not electrically connected internally. functional pin description (continued) pin name pin # description
isl78229 6 fn8656.3 february 12, 2016 submit document feedback hic/latch 37 this pin is used to select either hiccup or latch-of f response to faults including output overvoltage (monitoring th e fb pin), output undervoltage (monitoring the fb pin, default inactive), v in overvoltage (monitoring the fb pin), peak overcurrent protection (oc2), average current protection (monitoring the imon pin) and over-temperature protection (monitoring the ntc pin), etc. hic/latch = high to activate the hiccup fault response. hic/latch = low to have the latch-off fault response. either toggling the en pin or recyclin g vcc por resets the ic from latch-off status. refer to ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 for more details. atrk/dtrk 38 the logic input pin to select the input signal format options for the track pin. pull this pin high for the track pi n to accept analog input signals. pull this pin low for th e track pin to accept digital input signals. refer to ? digital/analog track function ? on page 26 for more details. rdt 39 a resistor connected from this pin to ground programs the dead times between ugx off to lgx on and lgx off to ugx on to prevent shoot-through. refer to ? driver configuration ? on page 25 for the selection of r dt . vcc 40 ic bias power input pin for the internal analog circuitry. a minimum 1f ceramic capacitor should be used between vcc and ground for noise decoupling purposes. vcc is typically biased by pvcc or an external bias supply with voltage ranging from 4.75v to 5.5v. since pvcc is providing pulsing drive current, a small resistor like 10 or smaller between pvcc and vcc can help to filter out the noises from pvcc to vcc. pad - bottom thermal pad. it is not used as an electrical connecti on to the ic. in layout it must be connected to pcb large groun d copper plane that doesn?t contain noisy power flows. put multiple vias (as many as possible) in this pad connecting to the ground copper plane to help reduce the ic?s ? ja . functional pin description (continued) pin name pin # description ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl78229arz isl7822 9arz -40 to +125 40 ld 6x6 wfqfn l40.6x6c isl78229ev1z evaluation board notes: 1. add ?-t? suffix for 4k unit or ?-t7a? suffix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau-ag plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), see device information page for isl78229 . for more information on msl see techbrief tb363 . table 1. key differences between family of parts part number topology pmbus? ntc track function package isl78229arz 2-phase boost controller yes yes yes 40 ld 6x6 wfqfn ISL78227ARZ 2-phase boost controller no no yes 32 ld 5x5 wfqfn
isl78229 7 fn8656.3 february 12, 2016 submit document feedback block diagram figure 3. block diagram vin_ov 5.2v ldo vin pvcc vcc ss ntc 1.2*vref_dac (default) 0.8*vref_dac (default) pgood vout_ov vout_uv gm1 atrk/dtrk vref_dac (1.6v default) fb comp addr1 clkout addr2 pllcomp fsync slope r2 q s r1 csa isen1p isen1n boot1 ug1 ph1 lg1 de/phdrp duplicate for each phase i sen1 105a oc2_ph1 sda i sen1 drop_phase2 sgnd 5a fault scl salert logic and registers vin/48 8-bit dac pvcc pgnd pgnd vref_trk de mode and phase drop mode selection imon 2v (default) oc_avg gm2 programmable adaptive dead time rdt rblank hic/latch lp filter track vref_2.5v 1k m u x ss clock v ramp 80a oc1_ph1 -48a oc_neg_ph1 i sen1 i sen1 2a i sen1 20a vco pll clock slope compensation i 2 c/pmbus interface atrak/ dtrk 48 por 1.2v en en en vin/48 otp pll soft-start delay and logic en_ss pwm control zcd_ph1 17a 3.47v vref_trk 0.3v ss hiccup /latch-off rising delay 1.1v phase_drop 1.6v (default) 1.21v vref_cc vref_ voutov 3 bits [2:0] d3h vref_ voutuv 3 bits [2:0] d4h 3 bits [2:0] d5h 112a 112a 8 i sen1 8 i sen2 iout n.c. pad v imon v fb v fb fault initialization delay 8 bits [7:0] 21h m u x v ntc v fb v imon 10-bit adc en_de phase drop control en_phase_drop hiccup retry delay default selection d2h latch-off logic ss_done en_hiccp en_latchoff i bias (ph1) (ph2) pwm comparator cmp_pd cmp_ocavg d cc en ot_ntc_warn vout_ov vout_uv oc_avg ot_ntc_fault vin_ov oc2_peak_ph1 oc2_peak_ph2 pllcomp_short vref_ ocavg 3 bits [2:0] d6h pll_lock ? ?
isl78229 8 fn8656.3 february 12, 2016 submit document feedback typical application - 2- phase synchronous boost figure 4. typical application - 2-phase synchronous boost isl78229 vcc boot1 ph1 ntc fb vout lg1 clkout pgood ug1 boot2 ph2 pgnd lg2 ug2 vin ss vin pvcc en track sda scl salert pmbus addr1 vin addr2 en_ic isen1n isen1p isen2n isen2p imon de/phdrp hic/latch comp vcc rdt vcc rblank atrk/dtrk sgnd fsync slope pvcc_bt pllcomp pvcc vcc r blank r dt r pll c pll1 c pll2 r slope c ss r fb2 r fb1 r cp c cp1 c cp2 c imon r imon r bias1b r set1b r bias1a r set1a c isen1 l1 l2 r sen1 r sen2 c pvcc c vcc r vcc r ntc r p_ntc r fs c boot1 c boot2 d boot2 d boot1 c in c in c out c out r bias2b r set2b r bias2a r set2a c isen2 power-good r pg q1 q2 q3 q4 atrk/dtrk: = vcc to track analog signal = gnd to track digital signal hic/latch: = vcc for hiccup mode = gnd for latchoff mode de/phdrp: = vcc for de mode = float for de and phase-drop mode = gnd for ccm mode clock_out 10f 0.47f 0.47f pvcc_bt r pvccbt 1f 6.8nf 1nf 220pf 220pf q1, q2, q3, q4: 2 buk9y6r0-60e in parallel 3.3k ?? 5.1 ?? 10 ?? 1m ?? 1m ??
isl78229 9 fn8656.3 february 12, 2016 submit document feedback absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v ph1, ph2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v boot1, boot2, ug1, ug2 . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.3v to +65.0v upper driver supply voltage, v boot - v ph . . . . . . . . . . . . . . . - 0.3v to +6.5v pvcc, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +6.5v isen1p, isen1n, isen2p, isen2n . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v v isenxp - v isenxn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to vcc + 0.3v esd rating human body model (tested per aec-q100-002) . . . . . . . . . . . . . . . . 2kv charged device model (tested per aec-q100-011) corner pins ( note 6 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n/a all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500v latch-up rating (tested per aec-q100-004) . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 40 ld 6x6 wfqfn package ( notes 4 , 5 ) . . 28 1.2 maximum junction temperature (plastic package). . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v to +55v pvcc, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75v to 5.5v ph1, ph2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +55v upper driver supply voltage, v bootx - v phx . . . . . . . . . . . . . . . . .3.5v to 6v isen1p to isen1n and isen2p to isen 2n differential voltage . . . . 0.3v isen1p, isen1n, isen2p, isen2n commo n-mode voltage . . . . 4v to 55v operational junction temperature rang e (automotive) . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. per aec-q100-011 paragraph 1.3.9, qfns have no corner pins. electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: vin = 12v, v pvcc = 5.2v, and v vcc = 5.2v, t a = -40c to +125c ( note 8 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit supply input input voltage range v in switching, under the condition of internal ldo having dropout (v in - pvcc) less than 0.25v 555 v input supply current to the vin pin (ic enabled) i q_sw en = 5v, v in = 12v, pvcc = v cc , boot1 and boot2 supplied by pvcc, r fsync = 40.2k (f sw = 300khz), lgx = open, ugx = open 8.0 10.0 ma i q_non-sw en = 5v, v in = 12v, pvcc = v cc , boot1 and boot2 supplied by pvcc, non-switching, lgx = open, ugx = open 6.0 8.5 ma input supply current to the vin pin (ic shutdown) i _sd_vin_55v en = gnd, vin = 55v 0.2 1.0 a input bias current (ic shutdown) to each of isen1p/isen1n/isen2p/isen2n pins i _sd_isenxp/n en = gnd, vin = 55v isen1p (or isen1n/isen2p/isen2n) = 55v -1 0 1 a input overvoltage protection vin ovp rising threshold (swi tching disable) en = 5v, v in rising 56.5 58.0 59.5 v vin ovp trip delay en = 5v, v in rising 5 s internal linear regulator ldo voltage (pvcc pin) v pvcc v in = 6v to 55v, c pvcc = 4.7f, i pvcc =10ma 5.0 5.2 5.4 v ldo saturation dropout voltage (pvcc pin) v dropout v in = 4.9v, c pvcc = 4.7f, i_pvcc = 80ma 0.3 v ldo current limit (pvcc pin) i oc_ldo v in = 6v, v pvcc = 4.5v 130 195 250 ma ldo output short current limit (pvcc pin) i ocfb_ldo v in = 6v, v pvcc = 0v 50 100 160 ma
isl78229 10 fn8656.3 february 12, 2016 submit document feedback power-on reset (for both pvcc and vcc) rising v vcc por threshold v porh_vcc 4.35 4.50 4.75 v falling v vcc por threshold v porl_vcc 4.05 4.15 4.25 v v vcc por hysteresis v porhys_vcc 0.4 v rising v pvcc por threshold v porh_pvcc 4.35 4.50 4.75 v falling v pvcc por threshold v porl_pvcc 3.0 3.2 3.4 v v pvcc por hysteresis v porhys_pvcc 1.3 v soft-start delay t ss_dly from por rising to initiation of soft-start. r fsync = 61.9k, f sw = 200khz, pllcomp pin network of r pll = 3.24k, c pll1 = 6.8nf and c pll2 = 1nf 0.85 ms en enable threshold v enh en rising 1.13 1.21 1.33 v v enl en falling 0.85 0.95 1.10 v v en_hys hysteresis 250 mv input impedance en = 4v 2 6m pwm switching frequency pwm switching frequency (per phase) f osc r fsync = 249k (0.1%) 46.0 50.2 54.5 khz r fsync = 82.5k (0.1%) 142 150 156 khz r fsync = 40.2k (0.1%) 290 300 310 khz r fsync = 10k (0.1%) 990 1100 1170 khz minimum adjustable switching frequency 50 khz maximum adjustable switching frequency 1100 khz fsync pin voltage 0.5 v minimum on-time (blanking time) on lgx t minon_1 minimum duty cycle, c ug = c lg = open r blank = 80k (0.1%) 315 410 525 ns t minon_2 minimum duty cycle, c ug = c lg = open r blank = 50k (0.1%) 175 260 325 ns t minon_3 minimum duty cycle, c ug = c lg = open r blank = 25k (0.1%) 100 140 180 ns t minon_4 minimum duty cycle, c ug = c lg = open r blank = 10k 75 90 105 ns maximum duty cycle d max d max = t_lg_ on/t sw , v comp = 3.5v, f sw = 300khz, r dt = 18.2k , c ug =open, c lg = open 88.5 89.0 90.5 % synchronization (fsync pin) minimum synchronization frequency at fsync input 50 khz maximum synchronization frequency at fsync input 1100 khz input high threshold vih 3.5 v input low threshold vil 1.5 v input minimum pulse width - rise-to-fall 20 ns electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: vin = 12v, v pvcc = 5.2v, and v vcc = 5.2v, t a = -40c to +125c ( note 8 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
isl78229 11 fn8656.3 february 12, 2016 submit document feedback input minimum pulse width - fall-to-rise 20 ns delay time from input pulse rising to lg1 rising edge minus dead time t dt1 c lg = open, r dt = 50k 35 ns input impedance input impedance before synchronization mode 1k input impedance after synchronization mode 200 m clkout clkout h i clkout = 500a vcc - 0.5 vcc - 0.1 v clkout l i clkout = -500a 0.1 0.4 v output pulse width c clkout = 100pf, t sw is each phase?s switching period 1/12 * t sw phase shift from lg1 rising edge to clkout pulse rising edge c lg1 = open, c clkout = open, f sw = 300khz, t dt1 = 60ns (refer to figure 65 on page 29 for the timing diagram) 87 soft-start soft-start current i ss 4.5 5.0 5.5 a minimum soft-start prebias voltage 0v maximum soft-start prebias voltage 1.6 v soft-start prebias voltage accuracy v fb = 500mv -25 0 25 mv soft-start clamp voltage v ssclamp 3.25 3.47 3.70 v hiccup retry delay (refer to ? fault response register set_fault_response (d2h) ? on page 35 for more details) hiccup retry delay if hiccup fault response selected 500 ms reference voltage for output voltage regulation system reference accuracy measured at the fb pin 1.576 1.600 1.620 v fb pin input bias current v fb = 1.6v, track = open -0.05 0.01 0.05 a error amplifier for output voltage regulation (gm1) transconductance gain 2ma/v output impedance 7.5 m unity gain bandwidth c comp = 100pf from comp pin to gnd 3.3 mhz slew rate c comp = 100pf from comp pin to gnd 3 v/s output current capability 300 a maximum output voltage 3.5 3.7 v minimum output voltage 0.1 0.3 v pwm core slope pin voltage 480 500 520 mv slope accuracy r slope = 20k (0.1%) -20 0 20 % r slope = 40.2k (0.1%) -20 3 20 % duty cycle matching v rsenx = 30mv, r setx = 665 (0.1%), r slope = 27k, f sw = 150khz, v comp = 2.52v, measure (t on_lg2 - t on_lg1 )/(t on_lg2 + t on_lg1 )*2 3% electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: vin = 12v, v pvcc = 5.2v, and v vcc = 5.2v, t a = -40c to +125c ( note 8 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
isl78229 12 fn8656.3 february 12, 2016 submit document feedback current sense amplifier minimum isenxn and isenxp common-mode voltage range accuracy becomes worse when lower than 4v 4v maximum isenxn and isenxp common-mode voltage range 55 v maximum input differential voltage range v isenxp - v isenxn 0.3 v isenxp/isenxn bias current i senxp/n_bias sourcing out of pin, en = 5v, v isenxn =v isenxp , v cm = 4v to 55v 100 123 150 a zcd detection - csa zero crossing detection (zcd) threshold v zcd_csa measures voltage threshold before r sen at csa inputs (equivalent to the voltage across the current sense shunt resistor), r set = 665 (0.1%) -4.0 1.3 6.0 mv phase dropping v imon phase-drop falling threshold, to drop phase 2 v phdrp_th_f when v imon falls below v phdrp_th_f , drop off phase 2 1.0 1.1 1.2 v v imon phase-add rising threshold, to add phase 2 v phadd_th_r when v imon rise above v phadd_th_r , add back phase 2 1.05 1.15 1.25 v v imon phase-drop thre shold hysteresis v phdrp_hys when v imon isl78229 13 fn8656.3 february 12, 2016 submit document feedback imon offset current v rsenx = 0v, r set = 665 (0.1%), with isenxp/n pins biased at 4v or 55v common-mode voltage 16 17 18 a constant current control reference accuracy vref cc measure the imon pin 1.575 1.600 1.625 v average overcurrent fault protection (oc_avg) (refer to ? average overcurrent fault (oc_avg) ? on page 38 for more details) oc_avg fault threshold at the imon pin 1.9 2.0 2.1 v oc_avg fault trip delay 1s gate drivers ug source resistance r ug_source 100ma source current, v boot - v ph = 4.4v 1.2 ug source current i ug_source v ug - v ph = 2.5v, v boot - v ph = 4.4v 2 a ug sink resistance r ug_sink 100ma sink current, v boot - v ph = 4.4v 0.6 ug sink current i ug_sink v ug - v ph = 2.5v, v boot - v ph = 4.4v 2.0 a lg source resistance r lg_source 100ma source current, pvcc = 5.2v 1.2 lg source current i lg_source v lg - pgnd = 2.5v, pvcc = 5.2v 2.0 a lg sink resistance r lg_sink 100ma sink current, pvcc = 5.2v 0.55 lg sink current i lg_sink v lg - pgnd = 2.5v, pvcc = 5.2v 3 a ug to ph internal resistor 50 k lg to pgnd internal resistor 50 k boot-ph uvlo detection threshold 2.8 3.0 3.2 v boot-ph uvlo detection threshold hysteresis 0.09 0.15 0.22 v dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 10k (0.1%) 55 70 85 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 10k (0.1%) 65 80 95 ns dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 18.2k (0.1%) 85 100 115 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 18.2k (0.1%) 95 110 125 ns dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 50k (0.1%) 185 210 240 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 50k (0.1%) 205 230 260 ns dead time delay - ug falling to lg rising t dt1 c ug = c lg = open, r dt = 64.9k (0.1%) 235 265 295 ns dead time delay - lg falling to ug rising t dt2 c ug = c lg = open, r dt = 64.9k (0.1%) 260 290 320 ns output overvoltage detection/protection (monitor the fb pin, refer to ? output overvoltage fault ? on page 36 for more details) fb overvoltage rising trip threshold v fbov_rise percentage of vdac output reference (default vref = 1.6v) selectable hiccup/latch-off response. 118 120 122 % fb overvoltage falling recovery threshold v fbov_fall percentage of vdac output reference (default vref = 1.6v) selectable hiccup/latch-off response. 114 116 118 % overvoltage threshold hysteresis 4% fb overvoltage trip delay 1us output undervoltage detection (monitor the fb pin, refer to ? output undervoltage fault ? on page 35 for more details) undervoltage falling trip threshold v fbuvref_fall percentage of vdac output reference (default vref = 1.6v) 78 80 82 % undervoltage rising recovery threshold v fbuvref_rise percentage of vdac output reference (default vref = 1.6v) 82.5 84.0 86.5 % electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: vin = 12v, v pvcc = 5.2v, and v vcc = 5.2v, t a = -40c to +125c ( note 8 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
isl78229 14 fn8656.3 february 12, 2016 submit document feedback undervoltage threshold hysteresis 4% power-good monitor (pgood pin) pgood leakage current pgood high, v pgood = 5v 1 a pgood low voltage pgood low, i pgood = 0.5ma 0.06 0.4 v pgood rising delay (de mode) the pgood rising delay from v sspin = v sspclamp (3.47v) and vref_trk 0.3v to pgood high when de mode is selected (de/phdrp = vcc or float) 0.5 ms pgood rising delay (ccm mode) the pgood rising delay from v sspin = v sspclamp (3.47v) and vref_trk 0.3v to pgood high when ccm mode is selected (de/phdrp = gnd) 100 ms pgood falling blanking time 10 s addr1, addr2, hic/latch, atrk/dtrk pin digital logic input input leakage current en <1v -1 1 a input pull-down current en >2v, pin voltage = 2.1v 0.7 1.0 2.0 a logic input low 0.8 v logic input high 2.1 v de/phdrp pin digital logic input (high/low/float) input leakage current -1 1 a float impedance - pin to vcc pin = gnd 100 200 300 k float impedance - pin to gnd pin = vcc 100 200 300 k output voltage on float pin pin = float 2.1 2.6 2.7 v tri-state input voltage max 3v tri-state input voltage min 1.8 v logic input low pin voltage falling 0.7 v logic input high pin voltage rising vcc - 0.4 v track pin - digital input logic input leakage current en <1v, pin voltage = 5v, v cc = 0v -1 1 a input pull-up current en >2v, pin voltage = 0v, v cc = 5v 0.8 1.1 1.5 a input pull-up current compliance voltage en >2v, pin open 2.5 v logic input low pin voltage falling 0.8 v logic input high pin voltage rising 2 v duty cycle conversion (fb accuracy) 0% duty cycle input, measure at the fb pin 0 v 25% duty cycle input, frequency = 400khz, measure at the fb pin 0.600 0.625 0.650 v 50% duty cycle input, frequency = 400khz, measure at the fb pin 1.218 1.253 1.288 v 60% duty cycle input, measure at the fb pin 1.45 1.49 1.53 v electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: vin = 12v, v pvcc = 5.2v, and v vcc = 5.2v, t a = -40c to +125c ( note 8 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
isl78229 15 fn8656.3 february 12, 2016 submit document feedback track pin - analog input input leakage current v track = 1.6v, leakage current into this pin to ground -1.0 -0.6 -0.3 a track input reference voltage range vref_dac = 1.6v 0 1.6 v track input reference voltage accuracy measure at the fb pin, v track = 1.5v -4.0 -0.5 4.0 % measure at the fb pin, v track = 0.5v -6.0 1.8 6.0 % track ss_done detection threshold 0.29 0.30 0.31 v pmbus? interface (scl and sda input pins) logic input voltage high 2.1 v logic input voltage low 0.8 v hysteresis 0.55 v sda output voltage low i out = -3ma 0.1 0.4 v input current 1 2 a input capacitance 5pf clock frequency 400 khz scl falling edge to sda valid time 1 s salert pin output output voltage low i out = -3ma 0.1 0.4 v output high leakage current v salert = 5.2v 0 1 a ntc pin input leakage current en <1v -1 0 1 a output sourcing current (from pin to ground) en >2v, pin voltage = 0v 19 20 21 a output current source compliance voltage en >2v vcc v default ntc warning threshold ntc pin voltage falling 450 mv default ntc fault protection thre shold ntc pin voltage falling 300 mv internal 8-bit dac minimum output voltage lsb = 8mv 8 mv maximum output voltage lsb = 8mv 2.048 v internal 10-bit adc (altenertively sampling voltages of ntc, fb, vin/48 and imon pins) minimum input voltage lsb = 2mv 2 mv maximum input voltage lsb = 2mv 2.048 v over-temperature protection over-temperature trip point 160 c over-temperature recovery threshold 145 c notes: 7. compliance to datasheet limits are assu red by one or more methods: production test, characterization and/or design. 8. the ic is tested in conditions with mini mum power dissipations in the ic meaning t a t j . electrical specifications refer to figure 3 on page 7 and typical application schematics ( page 8 ). operating conditions unless otherwise noted: vin = 12v, v pvcc = 5.2v, and v vcc = 5.2v, t a = -40c to +125c ( note 8 ). typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
isl78229 16 fn8656.3 february 12, 2016 submit document feedback performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. note: (see typical application in figure 4 on page 8 .) figure 5. efficiency vs load, 2-phase boost, 3 modes operation, f sw = 200khz, v in = 12v, v out = 36v, t a = +25c figure 6. en into preb iased output, ccm mode (de/phdrp = gnd), i out = 0a figure 7. en on and initialization to start-up, i out = 0a figure 8. soft-start, ccm mode (de/phdrp = gnd), i out =8a figure 9. en on and initialization to start-up, i out = 0a figure 10. soft-start, de+phdrop mode (de/phdrp = float), i out = 8a 50 55 60 65 70 75 80 85 90 95 100 0.01 0.10 1.00 10.00 100 .00 load current (a) de with phase drop de without phase drop ccm efficiency (%) ss 3.0v/div i l1 5.0a/div v out 1.0v/div with 36v offset ph1 30.0v/div 10ms/div pllcomp 500mv/div pvcc 2.0v/div ss 700mv/div ph1 30.0v/div 500s/div 20ms/div ss 3.0v/div pgood 5.0v/div v out 20.0v/div ph1 30.0v/div clkout 5.0v/div pvcc 2.0v/div pllcomp 500mv/div ss 2.0v/div 200s/div ss 3.0v/div pgood 5.0v/div v out 20.0v/div ph1 30.0v/div 5ms/div
isl78229 17 fn8656.3 february 12, 2016 submit document feedback figure 11. soft-start, de mode (de/phdrp = vcc), i out = 8a figure 12. en shutdown, pvcc/pgood/ss fall, i out = 0a figure 13. en shutdown, i out = 8a figure 14. ccm mode (de/ph drp = gnd), phase 1 inductor ripple current, i out = 0a figure 15. en shutdown, i out = 8a figure 16. ccm mode (de/ph drp = gnd), phase 2 inductor ripple current, i out = 0a performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) ss 3.0v/div pgood 5.0v/div v out 20.0v/div ph1 30.0v/div 5ms/div pvcc 2.0v/div pgood 3.0v/div ss 2.0v/div ph1 30.0v/div 20ms/div pgood 5.0v/div ph2 40.0v/div ph1 40.0v/div 20s/div v out 20.0v/div lg1 5.0v/div i l1 4.0a/div v out 30.0v/div 10s/div lg2 5.0v/div v out 20.0v/div pgood 4.0v/div ph2 30.0v/div ph1 30.0v/div 5ms/div lg1 5.0v/div i l2 4.0a/div v out 30.0v/div 10s/div lg2 5.0v/div
isl78229 18 fn8656.3 february 12, 2016 submit document feedback figure 17. de mode (de/phdr p = vcc), diode emulation operation, pulse skipping, i out = 0a figure 18. de mode (de/phdr p = vcc), diode emulation operation, i out = 29ma figure 19. de mode (de/phdrp = vcc), ph1 and ph2 diode emulation operation, pulse skipping, i out = 7ma figure 20. de+ph_drop mode (de/phdrp = float), ph1 diode emulation with ph2 dropped, i out = 29ma figure 21. de+phdrp mode (de/phdrp = float), ph1 diode emulation with ph2 dropped, i out = 7ma figure 22. de+phdrp mode (de/phdrp = float), ph2 added and dropped, under transient step load of 1a to 8a performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) v out 1.0v/div with 36v offset pgood 4.0v/div ph1 20.0v/div 5s/div ph2 20.0v/div ph2 30.0v/div ph1 30.0v/div 2s/div v out 10.0v/div ph2 30.0v/div ph1 30.0v/div 10s/div v out 10.0v/div ph1 30.0v/div ph2 30.0v/div 2s/div v out 10.0v/div ph1 30.0v/div ph2 30.0v/div 10s/div v out 10.0v/div ph2 30.0v/div ph1 30.0v/div 10ms/div imon 300mv/div i_load 5.0a/div
isl78229 19 fn8656.3 february 12, 2016 submit document feedback figure 23. analog tracking 10 0hz sinusoidal signal, ccm mode (de/phdrp = gnd), atrk/dtrak = vcc, i out = 1a figure 24. analog tracking 300hz sinusoidal signal at the track pin, ccm mode (de/phdrp = gnd), atrk/dtrak = vcc, i out = 1a figure 25. steady-state operation of input constant current mode, i in controlled at 43a constant, v out = 19.5v figure 26. digital tracking (tracking signal, frequency = 400khz, d = 0.5, v out = 28.3v figure 27. load current keep in creasing from no load to overload (25a), v out starts to drop when input constant current mode starts to work, input current is finally controlled to be constant figure 28. digital tracking (tracking signal, frequency = 400khz, d = 0.3), v out = 17v performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) fb 300mv/div track 300mv/div v out 6.8v/div ph1 20.0v/div 2ms/div fb 300mv/div track 300mv/div v out 6.8v/div ph1 20.0v/div 2ms/div v out 30.0v/div i_in 16a/div imon 500mv/div ph1 30.0v/div 50s/div v out 7.0v/div track 4.0v/div ph2 40.0v/div ph1 40.0v/div 1s/div v out 30.0v/div i_in 16a/div imon 500mv/div ph1 30.0v/div 1s/div v out 7.0v/div track 4.0v/div ph2 40.0v/div ph1 40.0v/div 1s/div
isl78229 20 fn8656.3 february 12, 2016 submit document feedback figure 29. digital tracking, (tracking signal, frequency = 200khz, d = 0.5), v out = 28.3v figure 30. de mode (de/phdrp = vcc), transient response, i out = 0.03 to 8a step load figure 31. ccm mode (de/phdrp = gnd), transient response, i out = 0 to 8a step load figure 32. shutdown via pmbus? command operation, off figure 33. de+ph_drop mode (de/phdrp = float), transient response, i out =1 to8a step load figure 34. enable via pmbus? command operation, on performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) v out 1.0v/div with 28v offset track 4.0v/div ph2 40.0v/div ph1 40.0v/div 10s/div ph2 30.0v/div i_load 5.0a/div v out 2.0v/div with 36v offset ph1 30.0v/div 10ms/div ph2 30.0v/div i_load 5.0a/div v out 1.0v/div with 36v offset ph1 30.0v/div 1ms/div pvcc 5.0v/div v out 30.0v/div sda 3.0v/div ph1 40.0v/div 2ms/div ph2 30.0v/div i_load 5.0a/div v out 1.0v/div with 36v offset ph1 30.0v/div 5ms/div pvcc 5.0v/div v out 30.0v/div sda 3.0v/div ph1 40.0v/div 5ms/div
isl78229 21 fn8656.3 february 12, 2016 submit document feedback figure 35. pmbus? command vout_command changes vref_dac from 1v to 1.6v. vout_transition_rate sets vref_dac changing slew rate at 12.5mv/ms figure 36. pmbus? command vout_command changes vref_dac from 1.6v to 1v. vout_transition_rate sets vref_dac changing slew rate at 200mv/ms figure 37. pmbus? command vout_command changes vref_dac from 1.6v to 1v. vout_transition_rate sets vref_dac changing slew rate at 12.5mv/ms figure 38. shutdown current at the vin pin i_sd vs temperature, v in = 55v figure 39. pmbus? command vout_command changes vref_dac from 1v to 1.6v. vout_transition_rate sets vref_dac changing slew rate at 200mv/ms figure 40. ic operational quiescent current vs temperature, ic switchin g, no load on lgx and ugx performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) ph2 40.0v/div v out 5.0v/div with 36v offset sda 4.0v/div ph1 40.0v/div 20ms/div ph2 30.0v/div v out 10.0v/div sda 4.0v/div ph1 30.0v/div 2ms/div ph2 40.0v/div v out 5.0v/div sda 4.0v/div ph1 40.0v/div 20ms/div 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 150 temperature (c) i_sd_vin (a) ph2 30.0v/div v out 10.0v/div sda 4.0v/div ph1 30.0v/div 2ms/div 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 temperature (c) iq_sw (ma)
isl78229 22 fn8656.3 february 12, 2016 submit document feedback figure 41. ic operational quiescent current vs temperature, ic not switching figure 42. v ref_cc system accuracy vs temperature, measured at the imon pin, vref_cc = 1.6v (default) figure 43. ntc pin output curr ent vs temperature, the ntc pin shorted to ground figure 44. imon output current accuracy (current sensing signal output) vs temperature, v rsenx = 30mv, r setx = 665 ? (0.1%) figure 45. vref_dac system accuracy vs temperature, measured at the fb pin, vref_dac = 1.6v (default) figure 46. internal ldo dropout voltage vs temperature, 80ma load current on ldo output (pvcc) performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 temperature (c) iq_non-sw (ma) 1.590 1.591 1.592 1.593 1.594 1.595 1.596 1.597 1.598 1.599 1.600 1.601 1.602 1.603 1.604 1.605 1.606 1.607 1.608 1.609 1.610 -50 -25 0 25 50 75 100 125 150 temperature (c) v ref_cc system accuracy (v) 15 16 17 18 19 20 21 -50 -25 0 25 50 75 100 125 150 temperature (c) i_ntc (a) 26.0 26.5 27.0 27.5 28.0 28.5 29.0 -50 -25 0 25 50 75 100 125 150 temperature (c) vin = 55v vin = 4v imon current (a) 1.590 1.591 1.592 1.593 1.594 1.595 1.596 1.597 1.598 1.599 1.600 1.601 1.602 1.603 1.604 1.605 1.606 1.607 1.608 1.609 1.610 -50 -25 0 25 50 75 100 125 150 temperature (c) vref_dac system accuracy (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 150 temperature (c) vdropout_ldo (v)
isl78229 23 fn8656.3 february 12, 2016 submit document feedback figure 47. internal ldo over current threshold and its foldback oc current vs temperature figure 48. v in ov rising threshold vs temperature figure 49. pvcc/vcc por rising threshold vs temperature figure 50. oc1 voltage threshold (across rsen) vs temperature figure 51. pvcc/vcc por falling threshold vs temperature figure 52. analog tracking reference system accuracy vs temperature, measured at the fb pin, v track =0.5v performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 -50 -25 0 25 50 75 100 125 150 temperature (c) ioc_ldo (ma) iocfb_ld o (ma) iocfb_ldo, ioc_ldo (mv) 55 56 57 58 59 60 -50 -25 0 25 50 75 100 125 150 temperature (c) vin_ov_rise (v) 4.2 4.3 4.4 4.5 4.6 -50 -25 0 25 50 75 100 125 150 temperature (c) vpor h_vcc (v) vporh_pvcc (v) vporh_pvcc, vporh_vcc (v) 30 35 40 45 50 55 60 -50-25 0 25 50 75100125150 temperature (c) voc1 (mv) 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 -50 -25 0 25 50 75 100 125 150 temperature (c) vporl_vcc (v) vporl_pvcc (v) vporl_pvcc, vporl_vcc (v) 0.5 0.7 0.9 1.1 1.3 1.5 -50 -25 0 25 50 75 1 00 125 150 temperature (c) analog track reference systeme accuracy_0.5v (%)
isl78229 24 fn8656.3 february 12, 2016 submit document feedback figure 53. analog tracking reference system accuracy vs temperature, measured at the fb pin, v track = 1.5v figure 54. digital tracking reference system accuracy vs temperature, measured at the fb pin, duty cycle of track pin signal is 0.5 figure 55. gate drive dead time vs temperature, r dt = 10k, t dt1 refers to ug falling to lg rising, t dt2 refers to lg falling to ug rising figure 56. gate drive deadtime vs temperature, r dt = 18.2k, t dt1 refers to ug falling to lg rising, t dt2 refers to lg falling to ug rising figure 57. ntc warning threshold (default) vs temperatur e figure 58. ntc fault threshold (default) vs temperature performance curves unless otherwise specified, operating conditions for the oscilloscope waveforms are v in = 12v, v out = 36v and t a = +25c. (continued) -3 -2 -1 0 1 2 3 -50 -25 0 25 50 75 100 125 150 temperature (c) analog track reference system accuracy_1.5v (%) 1.245 1.247 1.249 1.251 1.253 1.255 1.257 1.259 1.261 1.263 1.265 -50 -25 0 25 50 75 100 125 150 temperature (c) digital track reference system accuracy (v) 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 150 temperature (c) t dt 2 t dt 1 dead time (ns) 50 60 70 80 90 100 110 120 130 140 150 -50 -25 0 25 50 75 100 125 150 temperature (c) t dt 1 t dt 2 dead time (ns) 0.440 0.441 0.442 0.443 0.444 0.445 0.446 0.447 0.448 0.449 0.450 -50 -25 0 25 50 75 100 125 150 temperature (c) ntc warning threshold (default) 0.300 0.301 0.302 0.303 0.304 0.305 0.306 0.307 0.308 0.309 0.310 -50 -2 5 0 25 50 75 100 125 150 temperature (c) ntc fault threshold (default)
isl78229 25 fn8656.3 february 12, 2016 submit document feedback operation description the isl78229 is a 2-phase synchr onous boost controller with integrated drivers. it supports wide input and output ranges of 5v to 55v during normal operatio n and the vin pin withstands transients up to 60v. the isl78229 is integrated with 2a sourcing/3a sinking strong drivers to support high efficiency and high current synchronous boost applications. the drivers have a unique feature of adaptive dead time control of which the dead time can be programmed for different external mosfets, achieving both optimized efficiency and reliable mosfet driving. the isl78229 has selectable diode emulation and phase dropping functions for enhanced light-load efficiency. the pwm modulation method is a constant frequency peak current mode control (pcmc), which has benefits of input voltage feed-forward, a simpler loop to compensate compared to voltage mode control and inherent current sharing capability. the isl78229 offers a track functi on with unique features of accepting either digital or analog signals for the user to adjust reference voltage externally. the digital signal track function greatly reduces the complexity of the interface circuits between the central control unit and the boost regulator. equipped with cycle-by-cycle positive and nega tive current limiting, the track function can be reliably facilitated to achieve an envelope tracking feature in audio am plifier applications, which significantly improves system efficiency. in addition to the cycle-by-cycle current limiting, the isl78229 is implemented with a dedicated average constant current (cc) loop for input current. for devices having only peak current limiting, the average current under peak current limiting varies quite largely because the inductor ripple varies with changes of v in and v out and tolerances of f sw and inductors. the isl78229?s unique cc feature is able to have the average input current accurately controlled to be constant without shutdown. under certain constant input voltage, this means constant power limiting, which is especially useful for the boost converter. it helps the user optimize the system with the power devices? capability fully utilized by well controlled constant input power. with the pmbus? compliant di gital interface, the isl78229 provides the designer access to a number of useful system control parameters and diagnostic features. details of the functions are desc ribed in the following sections. synchronous boost in order to improve efficiency, the isl78229 employs synchronous boost architecture as shown in figure 4 on page 8 . the ugx output drives the high-side synchronous mosfet, which replaces the freewheeling diode and reduces the power losses due to the voltage drop of the freewheeling diode. while the boost converter is operat ing in steady state continuous conduction mode (ccm), each phase?s low-side mosfet is controlled to turn on with duty cycle d and ideally the upper mosfet will be on for (1-d). equation 1 shows the input to output voltage dc transfer function for boost is: driver configuration as shown in figure 4 on page 8 , the upper side ugx drivers are biased by the c bootx voltage between bootx and phx (where ?x? indicates the specific phase nu mber and same note applied throughout this document) . c bootx is charged by a charge pump mechanism. pvcc charges bootx through the schottky diode d bootx when lgx is high pulling phx low. bootx rises with phx and maintains the voltage to drive ugx as the d bootx is reverse biased. at start-up, the charging to c bootx from 0 to ~4.5v will cause pvcc to dip a little. so a typical 5.1 resistor r pvccbt is recommended between pvcc and d bootx to prevent pvcc from falling below vporl_pvcc. the typical value for c bootx is 0.47f. the bootx to phx voltage is monitored by uvlo circuits. when bootx-phx falls below a 3v threshol d, the ugx output is disabled. when bootx-phx rises back to be above this threshold plus 150mv hysteresis, the high-side driver output is enabled. for standard boost ap plication when upper side drivers are not needed, both ug1 and ug2 can be disabled by connecting either boot1 or boot2 to ground before part start-up initialization. phx should be connected to ground. programmable adaptive dead time control the ugx and lgx drivers are design ed to have an adaptive dead time algorithm that optimizes operation with varying operating conditions. in this algorithm, the device detects the off timing of lgx (ugx) voltages before turning on ugx (lgx). furthermore, the dead time between ugx on and lgx on can be programmed by the resistor at the rdt pin. the typical range of programmable dead time is 55ns to 200ns, or larger. this is intended for different external mosfets applications to adjust the dead time, maximizing the efficiency while at the same time preventing shoot-through. refer to figure 59 on page 26 for the selection of the rdt resistor and dead time, where t dt1 refers to the dead time between ug fa lling to lg rising, and t dt2 refers to the dead time between lg falling to ug rising. the dead time is smaller with a lower value rdt resistor, and it?s clamped to minimum 57ns when rdt is shorted to ground. since a current as large as 4ma will be pulled from the rdt pin if the rdt pin is shorted to ground, it is recommended to use 5k as the smallest value for the rdt resistor where the current drawing from the rdt pin is 0.5v/5k = 100a. v out v in 1d C ------------- = (eq. 1)
isl78229 26 fn8656.3 february 12, 2016 submit document feedback pwm control the isl78229 uses fixed frequency peak current mode control architecture. as shown in figure 3 on page 7 and the typical schematic diagram, error amplifier (gm1) compares the fb pin voltage and reference voltage and generates a voltage loop error signal at the comp pin. this er ror signal is compared with the current ramp signal (vramp) by the pwm comparator. the pwm comparator output combined with fixed frequency clock signal controls the sr flip-flop to generate the pwm signals (refer to ? peak current mode control ? on page 27 ). output voltage regulation loop the resistor divider r fb2 and r fb1 from v out to fb ( figure 4 on page 8 ) can be selected to set the desired v out . v out can be calculated by equation 2 : where in normal operation after start-up, v ref can be either vref_dac or vref_trk, whichever is lower. vref_dac default is 1.6v and can be programmed to a value between 0 - 2.04v via pmbus? command ? vout_command (21h) ? on page 48 . there are 3 inputs for the reference voltage for gm1: soft-start ramp ss, vref_trk and vref_dac. the gm1 uses the lowest value among ss, vref_trk and vref_dac. ss, vref_trk and vref_dac are valid for gm1 during and after soft-start. in general operation, vref_trk an d vref_dac are normally high before soft-start and ss normally ramps up from a voltage lower than vref_trk and vref_dac, so ss controls the output voltage ramp-up during soft-start. after soft-start is complete, the user can adjust vref_dac or vref_trk for the desired voltage. since vref_trk is valid before soft-start, to set vref_trk to be lower than ss can make the ss ramp ineffective since gm1 uses the lower vref_trk voltage. in such a case, the vref_trk becomes the real soft-start ramp that controls the output voltage ramp-up. digital/analog track function the track input provides an exte rnal reference voltage to be applied for the output voltage loop to follow, which is useful if the user wants to change the output voltage as required. an example is to employ envelope tracking technology in audio power amplifier applications. the is l78229 boost stage output is powering the audio power amplifier stage input, where the boost output tracks the music envelope signal applied at the track pin. ultimately, higher system efficiency can be achieved. the track pin can accept either a digital signal or an analog signal by configuring the atrk /dtrk pin to be connected to ground or vcc. figure 60 on page 27 shows the track function block diagram. vref_trk is fed into gm1 as one of the reference voltages. the gm1 takes the lowest voltage of ss, vref_trk and vref_dac as the actual reference. when vref_trk is the lowest voltage, it becomes the actual reference voltage for gm1 and the output voltage can be adjusted with track signal changes. regarding the effective vref_trk range: ? there is no limit for the minimum voltage on the track pin, but note the lower reference voltage and the lower voltage feedback regulation accuracy. note the ss_done signal is checking vref_trk 0.3v as one of the conditions (refer to t 8 -t 9 description on page 31 and figure 67 on page 30 ). also, for the boost converter, the re gulated output minimum voltage is usually the input voltage minus the upper mosfet?s body diode drop, in which case, the corresponding voltage at fb voltage is the minimum effective voltage for the vref_trk and vref_dac. ? the gm1 takes the lowest voltage of ss, vref_trk and vref_dac as the actual reference. the maximum effective range for vref_trk is determined by vref_dac or ss signal, whichever is lower. for example, after soft-start, when the ss pin equals to 3.4v(typical) and vref_dac = 1.6v (default), the maximum effective voltage for vref_trk is 1.6v. if ss = 3.47v and vref_dac = 2v, the maximum effective voltage for vref_trk is 2v. when atrk/dtrk = gnd (dtrk mode), the track pin accepts digital signal inputs. vref_trk (as one of the reference inputs for the error amplifier gm1) equals to the average duty cycle value of the pwm signal?s at the track pin. as shown in figure 60 on page 27 , the mux is controlled by the atrk/dtrk pin configurations. when atrk/dtrk = gnd, the mux connects the output of the q1 and q2 switch bridge to the input of a 2-stage rc filter (r 1 , c 1 , r 2 and c 2 ). the pwm signal at the track pin controls q1 and q2 to chop the 2.5v internal reference voltage. the phase node of q1 and q2 is a pwm signal with accurate 2.5v amplitude an d duty cycle d, where d is the input pwm duty cycle on the track input pin. the rc filter smooths out the pwm ac components and the voltage vref_trk after the rc filter be comes a dc voltage equaling to 2.5v * d: according to equation 3 , the pwm signals? am plitude at the track pin doesn?t affect the vref_trk accuracy and only the duty cycle value changes the vref_trk value. in general, the vref_trk reference accuracy is as good as the 2.5v reference. the built-in low figure 59. dead time vs rdt, t dt1 refers to ug falling to lg rising, t dt2 refers to lg falling to ug rising 0 50 100 150 200 250 300 5 10152025303540455055606570 rd t (k ? ) t dt 2 t dt 1 dead time, t dtx (ns) v out v ref 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 2) v reftrk 2.5 d ? = (eq. 3)
isl78229 27 fn8656.3 february 12, 2016 submit document feedback pass filter (r 1 , c 1 , r 2 and c 2 ) converts the pwm signal?s duty cycle value to a low noise reference. the low pass filter has cutoff frequency of 1.75khz and a gain of -40db at 400khz. the 2.5v pwm signal at phase node of q1 and q2 will have around 25mv at vref_trk, which is 1.56% of 1.6v reference. this will not affect the boost output voltage because of the limited bandwidth of the system. 400khz frequency is reco mmended for the pwm signal at the track pin. lower frequency at the track input is possible, but vref_trk will have higher ac ripple. bench test evaluation is needed to make sure the output voltage is not affected by this vref_trk ac ripple. when atrk/dtrk = vcc (atrk mode), the mux connects the track pin voltage to the input of the 2-stage rc filter r 1 /c 1 /r 2 /c 2 . in such a way, the track pin accepts analog signal inputs, with the gm1?s vref_trk input equal to the voltage on the track pin. it has the same low pass filter with a cutoff frequency of 1.75khz. if not used, the track pin should be left floating or tied to vcc and the internal vref_dac is working as the reference. the track function is enabled before the ss pin soft-start. the v out reference can be controlled by track inputs at start-up. after the ss pin ramps up to th e upper clamp and the vref_trk reaches 0.3v, the upper side fet is controlled to turn on gradually to achieve smooth transitions from dcm mode to ccm mode, of which transition duration is 100ms (when set at ccm mode). after this transition, pgood is allowed to be pulled high as long as when output voltage is in regulation (within ov/uv threshold). there is limitation of the maxi mum reference?s (vref_trk at figure 60 ) frequency for the boost output voltage being able to track, which is determined by the boost converter?s loop bandwidth. generally, the tracking reference signal?s frequency should be 10 times lower than the boost loop crossover frequency. otherwise, the boost output voltage cannot track the tracking reference sign al and the output voltage will be distorted. for example, for a boost converter with 4khz loop crossover frequency, the boost can track reference signals up to 400hz, typically. figures 23 and 24 on page 19 show performances tracking 100hz and 300hz signals. peak current mode control as shown in the figure 3 on page 7 , each phase?s pwm operation is initialized by the fixed clock for this phase from the oscillator (refer to ? oscillator and synchronization ? on page 29 ). the clocks for phase 1 and phase 2 are 180 out-of-phase. the low-side mosfet is turned on (lgx) by the clock (after dead time delay of t dt1 ) at the beginning of a pw m cycle and the inductor current ramps up. the isl78229?s current sense amplifiers (csa) sense each phase inductor current and generates the current sense signal i senx . the i senx is added with the compensating slope and generates v rampx . when v rampx reaches the error amplifier (gm1) output voltage, the pwm comparator is triggered and lgx is turned off to shut down the low-side mosfet. the low-side mosfet stays off until the next clock signal comes for the next cycle. after the low-side mosfet is turned off, the high-side mosfet turns on after dead time t dt2 . the turn-off time of the high-side mosfet is determined by either the pwm turn-on time at the next pwm cycle or when the inductor current become zero if the diode emulation mode is selected. multiphase power conversion for an n-phase interleaved multiphase boost converter, the pwm switching of each phase is distributed evenly with 360/n phase shift. the total combined current ripples at the input and output are reduced where smaller input and output capacitors can be used. in addition, it is benefici al to have a smaller equivalent inductor for a faster loop desi gn. also in some applications, especially in a high current case , multiphase makes it possible to use a smaller inductor for each phase rather than one big inductor (single-phase), which is sometimes more costly or unavailable on the market at the high current rating. smaller size inductors also help to achieve low profile design. the isl78229 is a controller fo r 2-phase interleaved converter where the 2 phases are operating with 180 phase shift, meaning each pwm pulse is triggered 1/2 of a cycle after the start of the pwm pulse of the previous phase. figure 61 illustrates the interleaving effect on input ripple current. the ac component of the two phase currents (i l1 and i l2 ) are interleaving each other and the combined ac current ripple (i l1 + i l2 ) at input are reduced. equivalently, the frequency of the ac inductor ripple at input is 2 times of the switching frequency per phase. figure 60. track function block diagram track vref_2.5v 1k 2m 2m 20pf 20pf m u x q1 q2 r 1 r 2 c 1 c 2 duty cycle = d 2.5*d gm1 vref_dac fb vref_trk ss comp atrk/dtrk atrak/ dtrk isl78229 internal circuits
isl78229 28 fn8656.3 february 12, 2016 submit document feedback to understand the reduction of the ripple current amplitude in the multiphase circuit, examine equation 4 representing an individual phase?s peak-to-peak inductor current. in equation 4 , v in and v out are the input and the output voltages respectively, l is the single-phase inductor value and f sw is the switching frequency. the input capacitors conduct the ripple component of the inductor current. in the case of a 2-phase boost converters, the capacitor current is the sum of the ripple currents from each of the individual phases. use equation 5 to calculate the peak-to-peak ripple of the total input current which goes through the input capacitors, where k p-p can be found in figure 62 under specific duty cycle. current sharing between phases the peak current mode control inherently has current sharing capability. as shown in figure 3 on page 7 , the current sense ramp v rampx of each phase are compared to the same error amplifier?s output at the comp pin by the pwm comparators to turn off lgx when v rampx reaches comp. thus, the v rampx peaks are controlled to be the same for each phase. v rampx is the sum of instantaneous induct or current sense ramp and the compensating slope. since the compensating slopes are the same for both phases, the inductor peak current of each phase is controlled to be the same. the same mechanism applies to the case when multiple isl78229s are configured in parallel for multiphase boost converter. basically, the comp pin of each isl78229 are tied together for each phase?s current sense ramp peak to be compared with the same comp voltage (v rampx = comp), meaning the inductor peak current of all the phases are controlled to be the same. the ? 4-phase operation ? section describes how to configure tw o isl78229 in parallel for a 4-phase interleaved boost converter. 4-phase operation two isl78229s can be used in parallel to achieve interleaved 4-phase operation. figure 63 shows the recommended configuration. the clkout from the master ic drives fsync of the slave ic to synchronize the switching frequencies. this achieves a 90 phase shift for the 4 phases switching, and the respective comp, fb, ss, en and imon pins of the two ics are connected. clkout is 90out-of-phase with the rising edge of lg1. therefore, the two phases of the second ic are interleaved with the two phases of the first ic. when using pmbus? functions for the two isl78229 operating in parallel, the telemetry functions as reading register information from the isl78229 will work fine. for example, the host can read via pmbus? for th e vin, fb, imon, ntc voltages, fault status and all other registers. the host only reads the information and does not chan ge the operating conditions. however, when using write commands to either control an isl78229 action (like operatio n on/off), or configure the fault protection response or th resholds, the designer should carefully evaluate the scenarios of the two ics operation in parallel. for example, it's recommended to configure both of the ics to have the same fault thresholds settings. otherwise, one of the ic's thresholds will not be ef fective. if any fault protection occurs (latch-off or hiccup), since the ss pins are connected together, the two ics' pwm switching will be shut off. generally, it's suggested to set the fault response to hiccup mode. when fault condition is gone, the two ic s can always restart to normal operations. figure 61. phase node and inductor-current waveforms for 2-phase converter i l1 180 t i l2 i l1 +i l2 t t i ppch v out v in C ?? v in lf sw v out ----------------------------------------------- = (eq. 4) i ppall k p-p i ppch ? = (eq. 5) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.4 5 0.5 0.55 0.6 0.65 0 .7 0.75 0.8 0.85 0.9 duty cycle figure 62. k p-p vs duty cycle k p-p figure 63. configurations for dual ic 4-phase operation master ic isl78229 slave ic isl78229 clkout fsync comp fb ss comp fb ss imon imon en en
isl78229 29 fn8656.3 february 12, 2016 submit document feedback oscillator and synchronization the switching frequency is determ ined by the selection of the frequency-setting resistor, r fsync , connected from the fsync pin to gnd. equation 6 is provided to assist in selecting the correct resistor value. where f sw is the switching frequency of each phase. figure 64 shows the relationship between r fsync and switching frequency. the isl78229 contains a phase lock loop (pll) circuit. refer to figure 4 on page 8 , the pll is compensated with a series resistor-capacitor (r pll and c pll1 ) from the pllcomp pin to gnd and a capacitor (c pll2 ) from pllcomp to gnd. at 300khz switching frequency, typical values are r pll =3.24k , c pll1 =6.8nf, c pll2 = 1nf. the pll locking time is around 0.7ms. generally, the same pll compensating network can be used in the frequency range of 50khz to 1.1mhz. with the same pll compensation network, at a frequency range higher than 500khz, the pll loop is overcompensated. however, the pll loop is stable just with slow frequency response. if a faster frequency response is required at a higher operating frequency, the pll compensation network can be tuned to have a faster response. an excel sheet to calculate the pll compensation is provided on the isl78229 web page. the isl78229?s switching frequency can be synchronized to the external clock signals applied at the fsync pin. the isl78229 detects the input clock?s rising ed ge and synchronizes the rising edge of lg1 to the input clock?s rising edge with a dead time delay of t dt1 . the switching frequency of each phase equals the fundamental frequency of the clock input at fsync. since the isl78229 detects only the edge of the input clock instead of its pulse width, the input clock?s pulse width can be as low as 20ns (as minimum), tens of ns, or hundreds of ns depending on the capability of the specific system to generate the external clock. the clkout pin outputs a clock si gnal with the same frequency of per phase switching freq uency. its amplitude is v cc and pulse width is 1/12 of per phase switching period (t sw /12). figure 65 shows the application example to put 2 isl78229, in parallel with the master ic?s clkout bein g connected to the fsync pin of the slave ic for 4-phase interleaved operation. the master ic outputs clkout signal with delay of (t sw /4-t dt1 ) after lg1_master. the slave ic fsync pin takes the clkout_master as the input and the slave?s ic lg1 is delayed by a time of (35ns + t dt1 ). therefore, the lg1_slave is delayed by (t sw /4 + 35ns) to lg1_master which is around 90 phase shift. with 90 phase shift between lg1 and respective lg2 for each ic, an interleaved 4-phases with 90 phase shift boost is achieved . once the isl78229 latches to be synchronized with the external clock, if the external clock on the fsync pin is removed, the switching frequency oscillator will shut down. then the part will detect pll_lock fault (refer to table 4 on page 41 ), and go to either hiccup mode or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 . if the part is set in hiccup mode, the part will restart with frequency set by the resistor at the fsync pin. the switching freq uency range of the isl78229 set by r fsync or by synchronization is typically 50khz to 1.1mhz. the low end 50khz is determined by pll_lock fault protection, which shuts down the ic when frequency is lower than 37khz typical (refer to table 3 on page 41 ). it?s viable to operate in frequency lower than 50khz by masking the pll_lock fault protection through pmbus? command ? fault_mask (d1h) ? on page 59 . the phase dropping mode is not allowed with external synchronization. minimum on-time (blank time) consideration the minimum on-time (also called blank time) of lgx is the minimum on pulse width as long as lgx is turned on and it is also intended for the internal circuits to blank out the noise spikes after lgx turns on. the t minon can be programmed by a resistor at the rblank pin. the selection of the t minon depends on 2 considerations. 1. the noise spike durations after lgx turns on, which is normally in a range of tens of ns to 100ns or longer depending on the external mosfet switch ing characteristic and noise coupling path to current sensing. (eq. 6) r fsync 2.49x 10 ?? 10 0.505 f sw -------------- - 5.5x10 8 C C ?? ?? = 0 50 100 150 200 250 300 0 100 200 300 400 500 600 700 800 900 100 0 110 0 f sw (khz) figure 64. f sw vs r fs r fsync (k?) figure 65. timing diagram of clkout vs lg1 and fsync vs lg1 (clkout_master connected to fsync_slave) lg1_ic_master clkout_ic_master fsync_ic_slave lg1_ic_slave t sw /4-t dt1 t1 t2 t3 35ns+t dt1
isl78229 30 fn8656.3 february 12, 2016 submit document feedback 2. ensure the charging of the boot capacitor during operations of lgx operating at t minon . one typical case is an operation when the input voltage is close to the output voltage. the duty cycle is smallest at t minon and c bootx is charged by pvcc via d bootx with short duration of t minon minus the delay to pull phase low. if such operation is required, especially when a large mosfet with large q g is used to support heavy load application, larger t minon can be programmed with the resistor at the rblank pin to ensure c bootx can be sufficiently charged during minimum duty cycle operation. refer to figure 66 for the selection of r blank resistor and t minon time. a 5k resistor is recommended as the minimum r blank resistor. operation initialization and soft-start prior to converter initialization, the en pin voltage needs to be higher than its rising threshold and the pvcc/vcc pin needs to be higher than the rising por thresh old. when these conditions are met, the controller begins in itialization and soft-start. figure 67 shows the isl78229 internal star t-up timing diagram from the power-up to soft-start. assuming input voltage is applied to the vin pin before t 1 and vcc is connected to pvcc, as shown on figure 67 , the descriptions for start-up procedure is elaborated in the following: t 1 - t 2 : the enable comparator holds the isl78229 in shutdown until the v en rises above 1.2v (typical) at the time of t 1 . during t 1 -t 2 v pvcc/vcc will gradually increase and reaches the internal power-on reset (por) rising th reshold 4.5v (typical) at t 2 . t 2 - t 3 : during t 2 - t 3 , the isl78229 will go through a self-calibration process to dete ct certain pin configurations (hic/latch, de/phdrp, atrk/dtrak) to latch in the selected operation modes. the time duration for t 2 - t 3 is typically 195s. t 3 - t 4 : during this period, the isl78229 will wait until the internal pll circuits are locked to the preset oscillator frequency. when pll locking is achieved at t 4 , the oscillator will generate output at the clk_out pin. the time duration for t 3 - t 4 depends on the pllcomp pin configuration. th e pll is compensated with a series resistor-capacitor (r pll and c pll1 ) from the pllcomp pin to gnd and a capacitor (c pll2 ) from pllcomp to gnd. at 300khz switching frequency, typical values are r pll = 3.24k , c pll1 = 6.8nf, c pll2 = 1nf. with this pllcomp compensation, the time duration for t 3 - t 4 is around 0.7ms. t 4 - t 5 : the pll locks the frequency t 4 and the system is preparing to soft-start. the isl78229 has one unique feature to prebias the ss pin voltage to be equal to v fb during t 4 - t 5 , which is around 50s. t 5 - t 6 : at t 5 the soft-start ramps up at the ss pin (v sspin ) and the comp voltage starts to ramp up as well. drivers are enabled but not switching during t 5 - t 6 since the comp is still below the current sense ramp offset. the device operates in diode emulation mode during soft-start period t 5 - t 8 . the slew rate of the ss ramp and the duration of t 5 - t 8 are determined by the capacitor used at the ss pin. figure 66. t minon vs r blank 0 50 100 150 200 250 300 350 400 450 500 5 1015202530354045 5055606570 r blank (k ? ) t minon (ns) en 1.2v por_r pvcc/vcc pllcomp clkout lg ug comp comp_ramp_offset vfb ss t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 pgood
isl78229 31 fn8656.3 february 12, 2016 submit document feedback t 6 - t 7 : at t 6 comp is above the current sense ramp offset and the drivers start switching. output voltage ramps up while fb voltage is following ss ramp during this soft-start period. at t 7 , output voltage reaches the regulation le vel and fb voltage reaches 1.6v (vref_dac default). t 7 - t 8 : ss continues ramping up until it reaches ss clamp voltage (v sspclamp ) 3.47v at t 8 indicating the ss pin ramp-up is completed. at t 8 , the isl78229 generates an internal ss_done signal, which goes high when both v sspin = v sspclamp (3.47v) and vref_trk 0.3v (as shown in figure 3 on page 7 ). this indicates the soft-start has completed. t 8 - t 9 : after t 8 , a delay time of either 0.5ms or 100ms is inserted before the pgood pin is released high at t 9 depending on the selected mode (refer to table 2 on page 34 ). 1. if the de/phdrp pin = gnd or float to have de mode selected, the pgood rising delay from v sspin = v sspclamp (3.47v) and vref_trk 0.3v to pgood rising is 0.5ms. 2. if the de/phdrp pin = gnd to have ccm mode selected, the pgood rising delay from v sspin = v sspclamp (3.47v) and vref_trk 0.3v to pgood rising is 100ms, during which period, the device is transiti oning from de mode to ccm mode. the high-side gate ugx is controlled to gradually increase the on time to finally merged with ccm on-time. this synchronous mosfet ?soft-on? feature is unique and ensures smooth transition fr om dcm mode to ccm mode after soft-start completes. more importantly, this ?sync fet soft-on? function eliminates the large negative current, which usually occurs when starting up to a high prebiased output voltage. this feature makes the system robust for all the challenging start-up conditio ns and greatly improves the system reliability. enable to enable the device, the en pin needs to be driven higher than 1.2v (typical) by the external en able signal or resistor divider between vin and gnd. the en pin has an internal 5m (typical) pull-down resistor. also, this pin internally has a 5.2v (typical) clamp circuit with a 5k (typical) resistor in series to prevent excess voltage applied to the intern al circuits. when applying the en signal using resist or divider from vin, internal pull-down resistance needs to be considered . also, the resistor divider ratio needs to be adjusted as its en pin input voltage may not exceed 5.2v. to disable or reset all fault status , the en pin needs to be driven lower than 1.1v (typical). when the en pin is driven low, the isl78229 turns off all of the bloc ks to minimize the off-state quiescent current. soft-start soft-start is implemented by an internal 5a current source charging the soft-start capacitor (c ss ) at ss to ground. the voltage on the ss pin slowly ramps up as the reference voltage for the fb voltage to follow during soft-start. typically, for boost converter before soft-start, its output voltage is charged up to be approximat ely a diode drop below the input voltage through the upper side mosfets? body diodes. to more accurately correlate the soft-start ramp time to the output voltage ramp time, the isl78229 ss pin voltage is prebiased with voltage equal to fb before soft-start begins. the soft-start ramp time for the boost output voltage ramping from v in to the final regulated voltage v outreg , can be calculated by equation 7 , where v ref is typically the vref_dac voltage (1.6v default) with the track pin tied high: pgood signal the pgood pin is an open-drain lo gic output to indicate that the soft-start period is completed, the input voltage is within safe operating range and the output vo ltage is within the specified range. the pgood comparator monitors the fb pin to check if output voltage is within 80% to 120% of reference voltage vref_dac (1.6v default). as described at the t 8 - t 9 duration in ? operation initialization and soft-start ? on page 30 , the pgood pin is pulled low during soft-start and it?s released high after ss_done with a 0.5ms or 100ms delay. pgood will be pulled low if any of the comparators for fb_uv, fb_ov or vin_ov is triggered fo r a duration longer than 10s. in normal operation after start-up, under fault recovery, the pgood will be released high with the same 0.5ms delay time after the fault is removed. current sense the isl78229 peak current cont rol architecture senses the inductor current continuously for fast response. a sense resistor is placed in series with the po wer inductor for each phase, and the isl78229 current sense amplif iers (csa) continuously sense the respective inductor current as shown in figure 69 by sensing the voltage signal across the sense resistor r senx (where ?x? indicates the specific phase nu mber and same note applied throughout this document) . the sensed current for each active figure 68. enable block en from external en control vcc 5m 5.2v clamp - + 1.2v to internal circuits 5k vin t ss v ref 1 v in v outreg ------------------------ C c ss 5 ? a ----------- ? ?? ?? ?? ? =
isl78229 32 fn8656.3 february 12, 2016 submit document feedback phase will be used for peak current mode control loop, phase current balance, individual phase cycle-by-cycle peak current limiting (oc1), individual phase overcurrent fault protection (oc2), input average constant current (cc) control and average overcurrent protection (oc_avg), diode emulation and phase drop control. the internal circuitry shown in figure 69 represents a single phase. this circuitr y is repeated for each phase. current sense for individual phase - i senx the rc network between r senx and isenxp/n pins as shown in figure 69 is the recommended configuration. the isenxp pin should be connected to the positive potential of the r sen_chx through resistor r setx , where in figure 69 r setx is composed by r setxa plus r setxb . r set is used to set the current sense gain externally. since there is an 112a bias current sinking to each of the isenxp and isenxn pins, r biasx with same value to r setx should be placed between the isenxn pin to the low potential of the r senx , where in figure 69 r biasx is composed by r biasxa plus r biasxb . it is recommended to have r setxa = r biasxa and r setxb =r biasxb , and insert a capacitor c isenx between them as shown in figure 69 . this will form a symmetric noise filter for the small current sense signals. the differential filtering time constant equals to (r setxa +r biasxa )*c isenx . this time constant is typically selected in range of tens of ns depending on the actual noise levels. csa generates the sensed current signal i senx by forcing isenxp voltage to be equal to isenxn voltage. since r setx equals to r biasx , the voltage drop across r setx and r biasx incurred by the fixed 112a bias current cancels each other. therefore, the resulting current at csa output i senx is proportional to each phase inductor current i lx . i senx per phase can be derived in equation 11 , where i lx is the per phase current flowing through r senx . r senx is normally selected with sm allest resistance to minimize the power loss on it. with r senx selected, r setx is selected by the desired cycle-by-cycle peak current limiting level oc1 (refer to ? peak current cycle-by-cycle limiting (oc1) ? on page 36 ). average current sense for 2 phases - imon the imon pin serves to monitor the total average input current of the 2-phase boost. as shown in figure 3 on page 7 , the individual current sense signals (i senx ) are divided by 8 and summed together. a 17a offset current is added to form a current source output at the imon pin with the value calculated as in equation 12 . assume r sen1 = r sen2 , r set1 = r set2 , and i in = i l1 +i l2 , which is the total boost input average current: as shown in figure 4 on page 8 , a resistor r imon is placed between the imon pin and ground, which turns the current sense output from the imon pin to a voltage v imon . a capacitor c imon should be used in parallel with r imon to filter out the ripple such that v imon represents the total average input current of the 2-phase boost. v imon can be calculated using equation 14 . as shown in figure 3 on page 7 , v imon is fed to inputs of gm2 and comparators of cmp_pd and cmp_ocavg for the following functions: 1. v imon is compared with 1.6v (vref_cc) at error amplifier gm2 inputs to achieve constant current control function. the cc control threshold for the boos t input current is typically set in a way that the per phase aver age inductor current (when cc control) is lower than the per phase cycle-by-cycle peak current limiting (oc1) threshold. refer to ? constant current control (cc) ? on page 37 for detailed descriptions. 2. v imon is compared with phase dr opping thresholds (1.1v falling to drop phase2, 1.15v rising to add phase2). refer to ? automatic phase dropping/adding ? on page 34 for detailed descriptions. figure 69. current sensing block diagram v in v out l i l isenxp i senx isenxn r senx r biasxa r biasxb r setxb i senx +112a r setxa csa 112a 112a i bias i senx isl78229 inte rnal circuits c isenx 112a + - + - + - + - + - r setx r setxa r setxb + = (eq. 8) r biasx r biasxa r biasxb + = (eq. 9) r biasx r setx = (eq. 10) i senx i lx r senx r setx ------------------ - ? = (eq. 11) imon i l1 r ? sen1 r set1 ------------------------------- - i l2 r ? sen2 r set2 ------------------------------- - + ?? ?? ?? 0.125 ? 17 10 ? 6 C + = (eq. 12) imon i in r sen r set --------------- - 0.125 ?? 17 10 ? 6 C + = (eq. 13) v imon imon r imon ? = (eq. 14)
isl78229 33 fn8656.3 february 12, 2016 submit document feedback 3. v imon is compared with 2v for oc_avg fault protections. refer to ? average overcurrent fault (oc_avg) ? on page 38 for detailed descriptions. the typical scenario when fast overloading is applied is described as the following. when large overload is suddenly applied at boost output, the phase inductor peak currents are initially limited by oc1 cycle-by-cycle, during which time the imon voltage slowly rises up due to the filter delay of r imon and c imon . when v imon reaches 1.6v, the cc loop starts to limit and control the average current to be constant, which lowers down the inductor current. as described previously, the cc threshold normally is set lower than the oc1 cycle-by-cycle limiting threshold. typically tens of nf are used for c imon . in the case when a longer time delay is needed, a larger c imon can be used. ? constant current control (cc) ? on page 37 has a more detailed description. adjustable slope compensation for a boost converter with peak current mode control, slope compensation is needed when duty cycle is larger than 50%. it is advised to add slope compensati on when the duty cycle is approximately 30 to 40% since a transient load step can push the duty cycle higher than the steady state level. when slope compensation is too low, the converter suffers from subharmonic oscillation, which may result in noise emissions at half the switching frequency. on the other hand, overcompensation of the slope may reduce the phase margin. therefore, proper design of the slope compensation is needed. the isl78229 features adjustab le slope compensation by setting the resistor value r slope from the slope pin to ground. this function will ease the compensation design and provide more flexibility in choosing the external components. figure 70 shows the block diagram related to slope compensation. for current mode control, in theory, the compensation slope slew rate m sl , needs to be larger than 50% of the inductor current down ramp slope slew rate m b . equation 15 shows the resistor value r slope at the slope pin to create a compensation ramp. where k slope is the selected gain of compensation slope over inductor down slope. for example, k slope = 1 gives the r slope value generating a compensation slope equal to inductor current down ramp slope. theoretically, the k slope needs to be larger than 0.5, but practically more th an 1.0 is used in the actual application. to cover the oper ating range, the maximum of v out and minimum of v in should be used in equation 15 to calculate the r slope . light-load efficiency enhancement for switching mode power supplies, the total loss is related to conduction loss and switching loss. at heavy load, the conduction loss dominates, while the switchin g loss dominates at light load condition. therefore, if a multiphase converter is running at a fixed phase number for the entire load range, the efficiency starts to drop significantly be low a certain load current. the isl78229 has selectable automatic phase dropping, cycle-by-cycle diode emulation and pulse skipping features to enhance the light-load efficiency. by observing the total input current on-the-fly and dropping an active phase, the system can achieve optimized efficiency over the entire load range. the phase dropping (ph_drop) and diode emulation (de) functions can be selected to be ac tive or inactive by setting the de/phdrp pin. refer to table 2 for the 3 configuration modes. 1. when de/phdrp = v cc , diode emulation function is enabled, and phase drop is disabled. 2. when de/phdrp = float, both diode emulation and phase drop functions are enabled. 3. when de/phdrp = gnd, both diode emulation and phase drop functions are disabled. the part is set in continuous conduction mode (ccm). r slope 6.67 10 5 ? l x r setx ?? k slope v out v in C ?? r ?? senx --------------------------------------------------------------- ------------------------ - ? ?? = (eq. 15) figure 70. slope compensation block diagram r slope slope v ramp r ramp i sl c sl vsl i slope = k2*0.5v/r slope lgx v ramp = (i senx +i sl )*r ramp i sl v ramp i sl0 i senx m b m sl m a m a1 = m a + m sl 0.5v v out l i l r senx r biasx r setx + - isenxp isenxn csa v in k1*i senx
isl78229 34 fn8656.3 february 12, 2016 submit document feedback automatic phase dropping/adding when the phase drop function is enabled, the isl78229 automatically drops or adds phase 2 by comparing the v imon to the phase dropping/adding thresholds. v imon is proportional to the average input current indicating the level of the load. the phase dropping mode is not allowed with external synchronization. phase dropping when load current drops and v imon falls below 1.1v, phase 2 is disabled. for better transient response during phase dropping, the isl78229 will gradually reduce the duty cycle of the phase from steady state to zero, typically within 8 to 10 switching cycles. this gradual dropping scheme will help smooth the change of the pwm signal and stabilize the system when phase dropping happens. from equations 13 and 14 , the phase dropping current threshold level for the total 2-phase boost input current can be calculated by equation 16 . phase adding the phase adding is decided by two mechanisms listed as follows. phase 2 will be added immediately if either of the 2 following conditions are met. 1. v imon > 1.15v, the imon pin voltage is higher than phase adding threshold 1.15v. the phase adding current threshold level for the total 2-phase boost input current can be calculated by equation 17 . 2. i senx > 80a (oc1), individual phase current triggers oc1. the first is similar to the phase dropping scheme. when the load increases causing v imon >1.15v, phase 2 will be added back immediately to support the increased load demand. since the imon pin normally has large rc filter and v imon is average current signal, this mechanism has a slow response and is intended for slow load transients. the second mechanism is intended to handle the case when load increases quickly. if the quick load increase triggers oc1 (i senx >80a) in either of the 2 ph ases, phase 2 will be added back immediately. after phase 2 is added, the phase dropping function will be disabled for 1.5ms. after this 1.5ms expires, the phase dropping circuit will be activated again and phase 2 can be dropped automatically as usual. diode emulation at light load condition when the diode emulation mode (de) is selected to be enabled (mode 1 and 2 in table 2 ), the isl78229 has cycle-by-cycle diode emulation operat ion at light load ac hieving discontinuous conduction mode (dcm) operation. with de mode operation, negative current is prevented and the conduction loss is reduced, therefore high efficiency can be achieved at light load conditions. diode emulation occurs during t 5 -t 8 (on figure 67 on page 30 ), regardless of the de/phdrp operating modes ( table 2 ). pulse skipping at deep light-load condition if the converter enters diode emulation mode and the load is still reducing, eventually pulse skipping will occur to increase the deep light-load efficiency. either phase 1 or phase 2, or both, will be pulse skipping at these deep light-load conditions. fault protections/indications the isl78229 is implemented with comprehensive fault protections, the majority of which can be monitored and programmed via pmbus?. faults/warnings manageable via pmbus? table 3 on page 41 summarizes all the type of faults/warnings accessible via pmbus? and the 3 related registers to monitor the fault status, enable/disable fa ult protecting reactions and program the desired type of fault responses (hiccup or latch-off). refer to section ? pmbus? user guide ? starting on page 40 for more details of the commands related to fault management. fault flag register fault_status (d0h) and salert signal when any of the faults in table 3 on page 41 occurs, the corresponding bit of fault_status register ( ? fault_status (d0h) ? on page 58 ) is set to 1 and the salert pin is pulled low, regardless if that type of fault is masked by the corresponding bit in the fault_mask register. the bits of the fault_status register status are kept unchanged as long as pvcc/vcc and en are high. even when the fault conditions are gone, the bit = 1 status will not be automatically cleared/reset to 0 by the device itself. each individual or multiple bits can be cleared/reset to 0, but only by a write command, or a clear_faults command via the pmbus?, or en/por recycling. refer to ? fault_status (d0h) ? on page 58 for more details of this pmbus? command, and table 3 on page 41 for fault related registers summary. salert pin the salert pin is an open-drain logic output and should be connected to vcc through a typical 10k resistor. when any bit of fault_status register is set to 1, the salert pin will be pulled low, regardless if that type of fault is masked by the corresponding bit in the fault_mask register. the host is interrupted by salert signal an d then inquire the isl78229 via pmbus? for informations about th e faults/warnings recorded in the fault_status register or any others to diagnose. table 2. ccm/de/ph_drop mode setting (de/phdrp pin) mode number (name) de/phdrp pin setting de mode phase-drop mode 1 (de) vcc enabled disabled 2 (de+ph_drop) float enabled enabled 3 (ccm) gnd disabled disabled (eq. 16) i inphdrp 1.1 r imon ------------------ - 17 10 ? 6 C C ?? ?? 8r set ?? r sen --------------------------------------------------------------- ------------------- a ?? = i inphadd 1.15 r imon ------------------ - 17 10 ? 6 C C ?? ?? 8r set ?? r sen --------------------------------------------------------------- ------------------- a ?? =
isl78229 35 fn8656.3 february 12, 2016 submit document feedback after the isl78229 is enabled, du ring the part initializing time t 1 - t 4 (refer to figure 67 on page 30 ) before soft-start, the salert pin is kept pulled low. if no faults (listed in table 4 on page 41 ) occurs during t 1 - t 4 , the salert pin open-drain transistor will be open at t 4 when soft-start begins and the pin voltage is pulled high by the external pull-up circuits. if any fault in table 4 on page 41 occurs after the beginning of soft-start, the corresponding bit of the fault_status register will be set to 1 and the salert pin will be pulled low. only when all the fault_status register bits are 0, the salert pin can be released to be pulled high. fault mask register fault_mask (d1h) when any of the faults in table 4 on page 41 are detected, the device will respond with either protecting actions (hiccup or latch-off) or ignoring this faul t depending on the corresponding bit setting of the fault_mask register ( ? fault_mask (d1h) ? on page 59 ). each bit of this register controls one specific fault condition to be ignored or not (refer to list in table 4 on page 41 ). the bit values are defined as follows: ? bit = 1 means to ignore, no protection action taken for the triggered fault, and the is l78229 keeps its normal pwm switching and operations. ? bit = 0 means to respond with protecting action to enter either hiccup or latch-off as fault response as described in ? fault response register set_ fault_response (d2h) ? . the register fault_mask has a default setting and can be programmed via pmbus? command ? fault_mask (d1h) ? on page 59 to set a specific fault?s prot ection response to be ignored or not. at default, the vout_uv fault is ignored with bit [6] set to 1 as default. refer to pmbus? command ? fault_mask (d1h) ? on page 59 for the details and table 3 on page 41 for fault related registers summary. fault response register set_fault_response (d2h) the fault response for each type of fault protection (listed in table 4 on page 41 ) can be programmed to be either hiccup or latch-off by setting the corresp onding bit of the register set_fault_response (ref er to pmbus? command ? set_fault_response (d2h) ? on page 60 and table 3 on page 41 ). ? when bit = 1, the fault protec tion response is hiccup mode ? when bit = 0, the fault protection response is latch-off mode the default bit values are determined by the hic/latch pin configuration as listed in the following. each bit value can be changed via pmbus? to set the resp ective bit of the fault response register (set_fault_response) at default: ? when the hic/latch pin is pulled high (vcc), the fault response will be hiccup mode. ? when the hic/latch pin is pulled low (gnd), the fault response will be latch-off mode. in hiccup mode, the device will stop switching when a fault condition is detected, and restart from soft-start after 500ms (typical). this operation will be repeated until fault conditions are completely removed. in latch-off mode, the device will stop switching when a fault condition is detected and pwm switching being kept off even after fault conditions are removed. in latch-off status, the internal ldo is alive to keep pvcc, and pmbus? interface is available for the user to monitor the type of fault triggered or other parameters. by either toggling the en pin or cycling vcc/pvcc below the por threshold will restart the system. refer to pmbus? command ? set_fault_response (d2h) ? on page 60 for details and table 3 on page 41 for fault related registers summary. input overvoltage fault as shown in figure 3 on page 7 , the isl78229 monitors the vin pin voltage divided by 48 (vin/48) as the input voltage information. this fault detection is active at the beginning of soft-start (t 5 as shown in figure 67 on page 30 ). the vin_ov comparator compares vin/48 to 1.21v reference to detect if vin_ov fault is triggered. equivalently, when v in >58v (for 5s), vin_ov fault event is triggered. the pgood pin will be pulled low and the corresponding bit (vin_ov, bit [2]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low. at the same time the vin_ov faul t condition is triggered, since the vin_ov fault protection respon se is enabled by default as the voin_ov bit (bit [2]) is set 0 by default in the fault_mask register (refer to ? fault mask register fault_mask (d1h) ? on page 35 and table 3 on page 41 ), the isl78229 will respond with fault protection actions to sh ut down the pwm switching and enters either hiccup or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 . the vin_ov fault protection can be disabled by setting the vin_ov bit (bit [2]) in ? fault mask register fault_mask (d1h) ? on page 35 to 1 via pmbus?. if disabled, there will be no fault protection actions when vin_ov fault is triggered, and the isl78229 will keep pwm swit ching and normal operation. under the selection of vin_ov fa ult protection activated with hiccup response, when the output voltage falls down to be lower than the vin_ov threshold 58v, the device will return to normal switching through hiccup soft-start. pgood will be released to be pulled high after a 0.5ms delay. as described in ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device itself and the salert pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults command via pmbus?, or en/por re cycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. output undervoltage fault the isl78229 monitors the fb pin voltage to detect if output undervoltage fault (vout_uv) occurs.
isl78229 36 fn8656.3 february 12, 2016 submit document feedback if the fb pin voltage is lower th an 80% (default) of the voltage regulation reference vref_dac, the vout_uv comparator is triggered to indicate vout_uv fault and the pgood pin will be pulled low. also, corresponding bit (vout_uv, bit [6]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low. when the output voltage rises back to be above the vout_uv threshold 80% vref_dac plus 4% hysteresis, pgood will be released to be pulled high after a 0.5ms delay. however, as described in the ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device itself and the sale rt pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults command via pmbus?, or en/por recycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. the vout_uv fault protection resp onse is disabled (ignored) by default as the vout_uv bit (bit [6]) is set 1 as default in the fault_mask register (refer to ? fault mask register fault_mask (d1h) ? on page 35 and table 3 on page 41 ), which means the isl78229 keeps the pwm switchin g and normal operation when vout_uv fault occurs. vout_uv fa ult protection can be enabled by setting set this vout_uv bit (bit [6]) to 0 in the ? fault mask register fault_mask (d1h) ? on page 35 . if enabled, the fault response can be programmed to be either hiccup or latch-off as described in ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 . the vout_uv threshold values can be set to 8 options based on percentage of the reference vref_dac via pmbus? command ? vout_uv_fault_limit (d4h) ? on page 62 . output overvoltage fault the isl78229 monitors the fb pin voltage to detect if output overvoltage fault (vout_ov) occurs. this fault detection is active at the beginning of soft-start (t 5 as shown in the figure 67 on page 30 ). if the fb pin voltage is higher th an 120% (default) of the voltage regulation reference vref_dac, the vout_ov comparator is triggered to indicate vout_ov fa ult and the pgood pin will be pulled low. the corresponding bit (vout_ov, bit [7]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low. at the same time, when a vout_ov fault condition is triggered, since the vout_ov fault protecti on response is enabled by default as the vout_ov bit (bit [7]) is set 0 by default in the fault_mask register (refer to ? fault mask register fault_mask (d1h) ? on page 35 and table 3 on page 41 ), the isl78229 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 . the vout_ov fault protection ca n be disabled by setting the vout_ov bit (bit [7]) in ? fault mask register fault_mask (d1h) ? on page 35 to 1 via pmbus?. if disabled, there will be no fault protection actions when vout_ov fault is triggered, and the isl78229 will keep pwm swit ching and normal operation. under the selection of vout_ov fa ult protection activated with hiccup response, when the output voltage falls down to be lower than the vout_ov threshold 120% vref_dac minus 4% hysteresis, the device will return to normal switching through hiccup soft-start. the pgood pin will be released to be pulled high after 0.5ms delay. however, as described in the ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device itself and the salert pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults command via pmbus?, or en/por re cycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. the vout_ov threshold values can be set to 8 options based on percentage of the reference vref_dac via pmbus? command ? vout_ov_fault_limit (d3h) ? on page 61 . overcurrent limiting and fault protection the isl78229 has multiple levels of overcurrent protection. each phase is protected from an overcurrent condition by limiting its peak current and the combined total current is protected on an average basis. also, each phase is implemented with cycle-by-cycle negative current limiting (oc_neg_th = -48a). peak current cycle-by-cycle limiting (oc1) each individual phase?s inductor peak current is protected with cycle-by-cycle peak current limiting (oc1) without triggering hiccup or latch-off shutdown of the ic. the controller continuously compares the csa output current sense signal i senx (calculated by equation 11 on page 32 ) to an overcurrent limiting th reshold (oc1_th = 80a) in every cycle. when i senx reaches 80a, the respective phase?s lgx is turned off to stop inductor current further ramping up. in such a way, peak current cycle-by-cycle limiting is achieved. the equivalent cycle-by-cycle peak inductor current limiting for oc1 can be calculated by equation 18 : negative current cycle-by-cycle limiting (oc_neg) each individual phase?s inductor current is protected with cycle-by-cycle negative current limiting (oc_neg) without triggering hiccup or latch-off sh utdown of the ic. the controller continuously compares the csa output current sense signal i senx (calculated by equation 11 on page 32 ) to a negative current limiting threshold (oc_neg_th = -48a) in every cycle. when i senx falls below -48a, the respective phase?s ugx is turned off to stop the inductor current further ramping down. in such a way, negative current cycle-by-cycle limiting is achieved. the equivalent negative inductor current limiting level can be calculated by equation 19 : (eq. 18) i oc1x 80 10 6 C r setx r senx ------------------ - a ?? ?? = i ocnegx 48 C 10 6 C r setx r senx ------------------ - a ?? ?? =
isl78229 37 fn8656.3 february 12, 2016 submit document feedback peak overcurrent fault (oc2_peak) if either of the two individual phase?s current sense signal i senx reaches 105a (oc2_th = 105a), the peak overcurrent fault (oc2_peak) event will be trigge red. this fault protection is intended to protect the device by shutdown (hiccup or latch-off) from a worst case condition where oc1 cannot limit the inductor peak current. this fault detection is active at the beginning of soft-start (t 5 as shown in the figure 67 on page 30 ). when an oc2_peak fault event is triggered, the corresponding bit (oc2_peak, bit [5]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low. at the same time, when an oc2_ peak fault event is triggered, since the oc2_peak fault protec tion response is enabled by default as the oc2_peak bit (bit [5]) is set 0 by default in the fault_mask register (refer to ? fault mask register fault_mask (d1h) ? on page 35 and table 3 on page 41 ), the isl78229 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 . the oc2_peak fault protection ca n be disabled by setting the oc2_peak bit (bit [5]) in ? fault mask register fault_mask (d1h) ? on page 35 to 1 via pmbus?. if disabled, there will be no fault protection actions when oc2_peak fault is triggered, and the isl78229 will keep pwm switching and normal operation. under the selection of oc2_peak fault protection activated with hiccup response, when both phases? peak current sense signal i senx no longer trip the oc2_peak thresholds (105a), the device will return to normal switching and regulation through hiccup soft-start. however, as described in the ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device it self and the salert pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults command via pmbus?, or en/por recycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. the equivalent inductor peak current threshold for the oc2_peak fault protection can be calculated by equation 20 : constant current control (cc) a dedicated constant average cu rrent control (cc) loop is implemented in the isl78229 to co ntrol the input current to be constant at overload conditions, which means constant input power limiting under a constant input voltage. as shown in figure 3 on page 7 , the v imon represents the average input current and is sent to the error amplifier gm2 input to be compared with the internal cc reference v ref_cc (which is 1.6v as default and can be programmed to different values via pmbus? command ? cc_limit (d5h) ? on page 63 ). gm2 output is driving comp voltage through a diode d cc . thus, the comp voltage can be controlled by either gm1 outp ut or gm2 output through d cc . at normal operation wi thout overloading, v imon is lower than the v ref_cc (1.6v at default). therefore, gm2 output is high and d cc is blocked and not forward conducting. the comp voltage is now controlled by the voltage loop error amplifier gm1?s output to have output voltage regulated. at input average current overloading case, when v imon reaches v ref_cc (1.6v at default), gm2 output falls and d cc is forward conducting, and gm2 output overri des gm1 output to drive comp. in this way, the cc loop overrides the voltage loop, meaning v imon is controlled to be constant achieving average constant current operation. under certain input voltage, input cc makes input power constant for the boost converter. compared to peak current limiting schemes, the average constant current control is more accurate to control the average current to be constant, which is beneficial for the user to accurately control the maximum average power for the converter to handle. the cc current threshold should be set lower than the oc1 peak current threshold with margin. ge nerally, the oc1 peak current threshold (per phase) is set 1.5 to 2 times higher than the cc current threshold (referred to as per phase average current). this matches with the physics of the power devices that normally have higher transient peak cu rrent rating and lower average current ratings. the oc1 provides protection against the transient peak current, which can be higher than the power devices can handle. the cc controls the average current with slower response, but with much more accurate control of the maximum power the system has to handle at overloading conditions. 1. when fast changing overloading occurs, since v imon has sensing delay of r imon *c imon , cc does not trip at initial transient load current until it reaches the cc reference 1.6v (default). oc1 will be triggered first to limit the inductor peak current cycle-by-cycle. 2. after the delay of r imon *c imon , when v imon reaches the cc reference 1.6v (default), the cc control starts to work and limit duty cycles to reduce the inductor current and keep the sum of the two phases? inductor currents being constant. the time constant of the r imon *c imon is typically on the order of 10 times slower than the voltag e loop bandwidth so that the 2 loops will not interfere with each other. cc loop is active at the beginning of soft-start. the cc threshold values can be set to 8 options via pmbus? command ? cc_limit (d5h) ? on page 63 , which ranges from 1.25v to 1.6v with a default setting of 1.6v. (eq. 20) i oc2x 105 10 6 C r setx r senx ------------------ - a ?? ?? =
isl78229 38 fn8656.3 february 12, 2016 submit document feedback average overcurrent fault (oc_avg) the isl78229 monitors the imon pin voltage (which represents the average current signal) to detect if average overcurrent (oc_avg) fault occurs. as shown in figure 3 on page 7 , the comparator cmp_ocavg compares v imon to 2v (as default) threshold. this fault detection is active at the beginning of soft-start (t 5 as shown in figure 67 on page 30 ). when v imon is higher than 2v, the oc_avg fault is triggered. the corresponding bit (oc_avg, bit [4]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low. the fault response at default is either hiccup or latch-off (as described in ? fault response register set_fault_response (d2h) ? on page 35 ). at the same time when an oc_avg fault condition is triggered, since the oc_avg fault protection response is enabled by default as the oc_avg bit (bit [4]) is set 0 by default in the fault_mask register (refer to ? fault mask register fault_mask (d1h) ? on page 35 and table 3 on page 41 ), the isl78229 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 . the oc_avg fault protection can be disabled by setting the oc_avg bit (bit [4]) in ? fault mask register fault_mask (d1h) ? on page 35 to 1 via pmbus?. if disabl ed, there will be no fault protection actions when oc_avg fault is triggered and the device will keep pwm switchin g and normal operation. under the selection of oc_avg fa ult protection activated with hiccup response, when the imon voltage falls down to be lower than the 2v (default) threshold, the device will return to normal switching through hiccup soft-start. as described in the ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device itself and the salert pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults command via pmbus?, or en/por recycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. the oc_avg fault threshold can be set to 8 options via pmbus? command ? oc_avg_fault_limit (d6h) ? on page 64 . external temperature monitoring and protection (ntc pin) the ntc pin allows temperature monitoring with a negative temperature coefficient (ntc) thermistor connected from this pin to ground. an accurate 20a current sourcing out of the ntc pin develops a voltage across the ntc thermistor, which can be converted to the celsius temperature due to the ntc thermistor characteristic. a precision resist or (100k, 0.1% for example) can be put in parallel with the ntc thermistor to linearize the voltage versus temperature ratio in certain range. as an example, to use a 100k re sistor in parallel with an ntc thermistor ntcs0805e3474fxt on the ntc pin, figure 71 shows the curve of the ntc pin voltage versus the temperature. the user can read the ntc pin voltage over pmbus? and converts the voltage to temperature using the curve in the chart. in the board layout, the ntc resistor should be placed in the area that needs the temperature to be monitored. typically the ntc is placed close to the power devices like mosfets to monitor the board temperature close to them. the voltage on the ntc pin is monitored for over-temperature warning (ot_ntc_warn) and over-temperature fault (ot_ntc_fault), both flagged by salert. the default threshold for ot warning is 450mv and the default threshold for ot fault is 300mv. both thresholds can be changed to different values via pmbus? commands ? ot_ntc_warn_limit (51h) ? on page 51 and ? ot_ntc_fault_limit (4fh) ? on page 50 . if ntc function is not used, the ntc pin should be connected to vcc. external over-temperature warning (ot_ntc_warn) if v ntc is lower than 450mv (default as determined by ot_ntc_warn_limit register), the ot_ntc_warn warning event is triggered. the correspo nding bit (ot_ntc_warn, bit [1]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low to deliver a warning to the host. the isl78229 continue s switching and regulating normally. there is no fault protection response when an ot_ntc_warn event is triggered. when the temperature drops and v ntc rises above 450mv (default), the ot_ntc_warn is no longer tripped. but as described in the ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device itself and the sale rt pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults co mmand via pmbus?, or en/por recycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. the ot_ntc_warn threshold ot _ntc_warn_limit values can be set to different values via pmbus? command ? ot_ntc_warn_limit (51h) ? on page 51 . this warning detection is active at the beginning of soft-start (t 5 as shown in figure 67 on page 30 ). figure 71. ntc voltage vs temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 10 0 11 012 0 13 0 14 0 15 0 v ntc (v) temperature ( c)
isl78229 39 fn8656.3 february 12, 2016 submit document feedback external over-temperature fault (ot_ntc_fault) if v ntc is lower than 300mv (default as determined by ot_ntc_fault_limit register), the ot_ntc_fault fault event is triggered. the corresponding bit (oc_ntc_fault, bit [3]) in the fault_status register ( ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41 ) is set to 1 and the salert pin is pulled low to deliver a warning to the host. when the ot_ntc_fault fault condition is triggered, since the ot_ntc_fault fault protection resp onse is disabled by default as the ot_ntc_fault bit (bit [3]) is set 1 by default in the fault_mask register (refer to ? fault mask register fault_mask (d1h) ? on page 35 and table 3 on page 41 ), the isl78229 will not respond with fault protec tion actions and the isl78229 continues switching and regulating normally. the ot_ntc_fault fault protection can be enabled by setting the ot_ntc_fault bit (bit [3]) in ? fault mask register fault_mask (d1h) ? on page 35 to 0 via pmbus?. if enabled, the isl78229 will respond with fault protection actions to shut down the pwm switching and enters either hiccup or latch-off mode as described in ? fault response register set_fault_response (d2h) ? on page 35 and table 3 on page 41 . under the selection of ot_ntc_fault fault protection activated with a hiccup response, when the temperature drops and v ntc rises back to be above 300mv (default), the ot_ntc_fault is no longer tripped, and the device will return to normal switching through hiccup soft-start. however, as described in the ? fault flag register fault_status (d0h) and salert signal ? on page 34 , the bit = 1 status in the fault_status register will not be automatically cleared/reset to 0 by the device itself and the salert pin is kept low. the bits in the fault_status register can only be cleared to 0 by a write command, or clear_faults command via pmbus?, or en/por recycling. when all the bits in the fault_status register are 0, the salert pin is released to be pulled high. the ot_ntc_fault threshold values can be set to different values via pmbus? command ? ot_ntc_fault_limit (4fh) ? on page 50 . this warning detection is active at the beginning of soft-start (t 5 as shown in the figure 67 on page 30 ). internal die over-temperature protection the isl78229 pwm will be disabled if the junction temperature reaches +160c (typical) while the internal ldo is alive to keep pvcc/vcc biased (vcc connected to pvcc). a +15c hysteresis ensures that the device will restart with soft-start when the junction temperature falls below +145c (typical). internal 5.2v ldo isl78229 has an internal ldo with input at vin and a fixed 5.2v/100ma output at pvcc. the internal ldo tolerates an input supply range of vin up to 55v (60v absolute maximum). a 10f, 10v or higher x7r type of ceramic capacitor is recommended between pvcc to gnd. at low vin operation when the internal ldo is saturated, the dropout voltage from the vin pin to the pvcc pin is typically 0.3v under 80 ma load at pvcc as shown in the ?electrical specifications? table on page 9 . this is one of the constraints to estimate the required minimum vin voltage. the output of this ldo is mainly used as the bias supply for the gate drivers. with vcc connected to pvcc as in the typical application, pvcc also supplies othe r internal circuitry. to provide a quiet power rail to the internal analog circuitry, it is recommended to place an rc filter between pvcc and vcc. a minimum of 1f ceramic capacitor from vcc to ground should be used for noise decoupling pu rpose. since pvcc is providing noisy drive current, a small resistor like 10 or smaller between the pvcc and vcc helps to prevent the noises interfering from pvcc to vcc. figure 72 shows the internal ldo?s output voltage (pvcc) regulation versus its output current. the pvcc will drop to 4.5v (typical) when the load is 195ma (typical) because of the ldo current limiting circuits. when the load current further increases, the voltage will drop further and finally enter current foldback mode where the output current is clamped to 100ma (typical). at the worst case when ldo output is shorted to ground, the ldo output is clamped to 100ma. based on the junction to am bient thermal resistance r ja of the package, the maximum junction temperature should be kept below +125c. however, the power losses at the ldo need to be considered, especially when the gate drivers are driving external mosfets with large gate charges. at high v in , the ldo has significant power dissipation that may raise the junction temperature where the thermal shutdown occurs. with an external pnp transistor as shown in figure 73 on page 40 , the power dissipation of the internal ldo can be moved from the isl78229 to the external transistor. choose r s to be 68 so that the ldo delivers about 10ma when the external transistor begins to turn on. the external circuit increases the minimum input voltage to approximately 6.5v. figure 72. internal ldo output voltage vs load 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00 0.05 0.10 0.15 0.20 0.25 iout_pvcc (a) v_pvcc (v)
isl78229 40 fn8656.3 february 12, 2016 submit document feedback pmbus? user guide the isl78229 is implemented with a pmbus? digital interface for the user to monitor and chan ge a few operating parameters allowing smart contro l of the regulator. the power management bus (pmbus?) is an open-standard digital power management protocol. it uses smbus as its physical communication layer and includes support for the smbus alert (salert). in much the same way as smbus defines the general means to manage po rtable power, pmbus? defines the means to manage power subsystems. pmbus? and smbus are i 2 c derived bus standards that are generally electrically compatible with i 2 c. they are more robust (timeouts force bus reset) and offer more features than i 2 c, like smbalert(salert) line for interrupts, packet error checking (pec) and host notify protocol. the isl78229 is compliant with the pmbus? power system management protocol specification part i and ii version 1.2. these specification documents may be obtained from the website http://pmbus?.org/home . these are required reading for complete understanding of the pmbus? implementation. ?specification part i ? genera l requirements transport and electrical interface - includes the general requirements, defines the transport and elec trical interface and timing requirements of hardwired signals. ? specification part ii ? command language - describes the operation of commands, data fo rmats, fault management and defines the command language used with the pmbus?. monitor operating parameters via pmbus? a system controller can monitor several isl78229 operating parameters through the pmbus? interface including: ? input voltage (monitors the vin pin) ? output voltage (monitors the fb pin) ? input current (monitors the imon pin) ? external temperature (monitors the ntc pin) monitor faults and configure fault responses when any of the 10 fault conditions in table 4 on page 41 occur, the corresponding bit of the fault_status register will be set to 1 and the salert pin will be pulled low, regardless whether that type of fault is masked by the fault_mask register . the pmbus? host controller will get interrupted by monitoring the salert pin and respond as follows: ? isl78229 device pulls salert low. ? pmbus? host detects that salert is low, then performs transmission with alert response address to find which device is pulling salert low. ? pmbus? host talks to the device that is pulling salert low. the actions that the host performs next are up to the system designer. each individual bit of the fault_status register can only be cleared to 0 by writing to that register via pmbus?, or by clear_faults command, or por recycle. when all the bits of fault_status register are reset to 0, the salert pin is release to be pulled high. table 4 on page 41 lists the 10 types of faults that can be accessed through pmbus? to: ? monitor or reset/clear each indi vidual bit of the fault_status register (d0h) for its corre sponding fault's status. ? configure the fault_mask register (d1h) to ignore or not to ignore each individual fault's protection. ? configure the set_fault_response register (d2h) to set each individual fault respon se to hiccup or latch-off. refer to ? pmbus? command detail ? starting on page 46 for details on each specific pmbus? command. set operation/fault thresholds via pmbus? a system controller can change the isl78229 operating parameters through the pmbus? interface. below are some commands but not limited to: ? enable or disable the pwm operation and regulation ?set output voltage ? set output voltage changing slew rate ? set output overvoltage thresholds ? set output undervoltage thresholds ? set input constant current control thresholds accessible timing fo r pmbus? registers status all the pmbus? command registers are set to default values during the part initialization period during t 2 - t 3 in figure 67 on page 30 . all the pmbus? registers (c ommands) are ready to be accessed after this part initialization period. after part start-up, as long as en and pvcc/vcc is kept high, all the pmbus? registers values are accessible via the pmbus?. when the part is in latch-off status or hiccup mode triggered by any fault in table 4 on page 41 , the internal ldo is still enabled and keeps pvcc/vcc high. all the pmbus? register values are accessible via pmbus?, the fault_status register values are accessible for the host to diagnose the type of fault. either en low or pvcc/vcc falling below por will disable the isl78229 and all the registers ar e reset and not accessible via pmbus?. figure 73. supplementing ldo current vin pvcc vin pvcc isl78229 r s
isl78229 41 fn8656.3 february 12, 2016 submit document feedback table 3. registers to monitor fault status and configure fault response command code register name format access descriptions default value refer to page d0h fault_status bit field r/w 1: fault occurred 0: no fault see table 4 page 58 d1h fault_mask bit field r/w 1: ignore fault with no protection response 0: hiccup or latch-off fault response see table 4 page 59 d2h set_fault_response bit field r/w 0: latch-off 1: hiccup see table 4 page 60 table 4. fault names list for the registers (with default values) in table 3 fault name bit number d0h default value d1h default value d2h default value set by hic/latch pin hic/latch = gnd: bits [9:0] = 00000000 hic/latch = vcc: bits [9:0] = 11111111 related fault to be monitored/controlled cml 0 0 1 set by the hic/latch pin communications warning (for unsupported command, pec error) ot_ntc_warn 1 0 0 set by the hic/latch pin external over-temperature warning (ntc_pin<450mv as default, threshold programmable) vin_ov 2 0 0 set by the hic/latch pin input overvoltage fault (vin_pin>58v) ot_ntc_fault 3 0 1 set by the hic/latch pin external over-temperature fault (ntc_pin<300mv as default, threshold programmable) oc_avg 4 0 0 set by the hic/latch pin input average overcurrent fault (imon_pin> 2v) oc2_peak 5 0 0 set by the hic/latch pin peak overcurrent fault (i senx >105a) vout_uv 6 0 1 set by the hic/latch pin output un dervoltage fault (fb_ pin<80%vref_dac as default, threshold programmable) vout_ov 7 0 0 set by the hic/latch pin output ov ervoltage fault (fb_pin>120%vref_dac as default, threshold programmable) pllcomp_short 8 0 0 set by the hic/latch pin pllcomp pin shorted to high potential voltages (pllcomp_pin>1.7v) pll_lock 9 0 0 set by the hic/latch pin pll loop fault due to reaching minimum frequency (detect the minimum frequency of 37khz as typical)
isl78229 42 fn8656.3 february 12, 2016 submit document feedback device identification address and read/write the isl78229 serves as a slave device on the pmbus?. the 7-bit physical slave address can be set by the addr1 and addr2 pin configurations to have 4 address options. table 5 defines the 4 available 7-bit addresses for the isl78229 where the bits [7:3] are fixed and bits [2:1] are dete rmined by the addr1 and addr2 pin configurations. bit [0] is r/ w bit to define the command to perform read (bit = 1) or write (bit = 0). pmbus? data formats used in isl78229 the data format used in the isl78229 are listed below. 16-bit linear unsigned (16lu) 16-bit linear unsigned (16lu) data format is a two byte (16-bit) unsigned binary integer. for isl7 8229, the 16lu data format is used to: read the 16lu data to report the 10-bit adc input voltage the 16lu data format is used in some commands to report the binary unsigned integer data at the 10-bit adc output, where the bits [15:10] are not used and bits [9:0] are used and equals to the 10-bit adc output unsigned binary integer value. the input of the adc is alternatively connected to voltages of ntc, fb, vin/48 and imon pins for monitoring. the adc has 2mv for 1 lsb. so the 16lu data can report voltage range of 0v to 2.046v (2mv*(2 10-1 )). equation 21 can be used to convert the 16lu data reported by the commands to adc input voltage, where command is the 10-bit [9:0] unsigned binary integer value: the 10-bit adc accuracy from output to input has typical tolerances of -15mv to +25mv over the adc input range of 0v to 2.046v. write/read the 16lu data as the 8-bit dac input the 16lu data format is used in command ? vout_command (21h) ? on page 48 to set or read the 8-bit dac input binary unsigned integer data which changes the dac output voltage. the dac output voltage is vref_dac, which is the reference to the output voltage regulation. in this command, the 8-bit [7:0] unsigned binary integer value are used and equal to the 8-bit dac output binary integer value. the dac has 8mv for 1 lsb. so the 16lu data can set vref_dac voltage range of 0v to 2.04v (8mv*(2 8-1 )). equation 22 can be used to convert the 16lu data written/read by the vout_command to dac output voltage, where command is the 8-bit [7:0] unsigned binary integer value in the command: write/read the 16lu data to set ntc threshold the 16lu data format is used in command ? ot_ntc_fault_limit (4fh) ? on page 50 and ? ot_ntc_warn_limit (51h) ? on page 51 to set the ot_ntc_warn and ot_ntc_fault thresholds. the 10-bit [9:0] unsigned binary integer values are used and the 1 lsb represents 2mv. equation 23 can be used to convert the 16lu data in the ot_ntc_fault_limit and ot_ntc_warn_limit commands to the voltage thresholds for the ntc pin, where command is the 10-bit [9:0] unsigned binary integer value in the command: bit field (bit) breakdown of bit field is provided in ? pmbus? command detail ? starting on page 46 . custom (cus) breakdown of custom data format is provided in ? pmbus? command detail ? starting on page 46 . a combination of bit field and integer are common type of custom data format. table 5. slave address set by the addr1 and addr2 pin configurations addr1/addr2 setting device identification -slave address bits 7-1 r/w bit bit 0 addr1 addr2 bit field 7654321 0 gnd gnd 1001100write: 0 read: 1 gnd vcc 1001110write: 0 read: 1 vcc gnd 1001101write: 0 read: 1 vcc vcc 1001111write: 0 read: 1 v adcin 0.002 command ? = (eq. 21) v dacout 0.008 command v refdac = ? = (eq. 22) v otntc 0.002 command ? = (eq. 23)
isl78229 43 fn8656.3 february 12, 2016 submit document feedback pmbus? command summary table 6 lists all the command sets available in isl78229. refer to ? pmbus? command detail ? starting on page 46 for details on each specific pmbus? command. table 6. pmbus? command summary command code command name access number of data bytes data format default setting descriptions refer to page 01h operation read/write byte 1 bit 80h enable/disable page 46 03h clear_faults send byte 0 n/a n/a clears any faul t bits in the fault_status register that have been set page 46 10h write_protect read/write byte 1 bit 00h protections against accidental changes page 47 19h capability read byte 1 bit b0h provides the way for a host system to determine some key capabilities of isl78229 as pmbus? device page 47 21h vout_command read/write word 2 16lu 00c8h sets nominal reference voltage for v out set-point, vref_dac = 1.6v as default page 48 27h vout_transition_rate read/write word 2 bit 0004h sets v out transition rate during vout_command commands to change v out . page 49 4fh ot_ntc_fault_limit read/write word 2 16lu 0096h sets the over-temperature fault limit, ntc_pin <300mv as default page 50 51h ot_ntc_warn_limit read/write word 2 16lu 00e1h sets the over-temperature warning limit, ntc_pin <450mv as default page 51 88h read_vin read word 2 16lu n/a reports input voltage measurement (vin_pin/48) page 52 89h read_vout read word 2 16lu n/a reports th e fb pin voltage measurement which is proportional to output voltage page 53 8ch read_iin read word 2 16lu n/a intersil defined register. reports the imon pin voltage measurement which represents the total two phases? inductor average current which is the boost input current. page 54 8dh read_temperature read word 2 16lu n/a repor ts the ntc pin voltage measurement which represents the temperature page 55 98h pmbus_revision read byte 1 bit 22h reports the pmbus? revision to which the isl78229 is compliant. (pmbus? part i revision 1.2, part ii revision 1.2) page 56 adh ic_device_id read word 2 cus 8229h report s device identification information page 56 aeh ic_device_rev read word 2 cus 0c01h rep orts device revision information page 57
isl78229 44 fn8656.3 february 12, 2016 submit document feedback d0h fault_status read/write word 2 bit 0000h intersil defined register. each bit?s value records one specific fault or warning event (as listed below) being triggered or not. bits [15:10]: unused bit [9]: pll_lock fault bit [8]: pllcomp_short fault bit [7]: vout_ov fault bit [6]: vout_uv fault bit [5]: oc2_ipeak fault bit [4]: oc_avg fault bit [3]: ot_ntc_fault fault bit [2]: vin_ov fault bit [1]: ot_ntc_warn warning bit [0] cml warning fault_status bit = 1 stays unchanged until using a write command to set bit = 0, write clear fault command or por cycle. fault_status is not masked by fault_mask register. page 58 d1h fault_mask read/write word 2 bit 0049h intersil defined register. each bit controls one specific fault condition listed below to be masked (ignored) or not. bits [15:10]: not used bit [9]: ignore pll_lock fault bit [8]: ignore pllcomp_short fault bit [7]: ignore vout_ov fault bit [6]: ignore vout_uv fault bit [5]: ignore oc2_ipeak fault bit [4]: ignore oc_avg fault bit [3]: ignore ot_ntc_fault fault bit [2]: ignore vin_ov fault bit [1]: not used bit [0]: not used bit = 1 means to ignore, no protecting action taken by the device for the triggered fault, and the isl78229 keeps its normal pwm switching and operations. bit = 0 means to respond with protecting action to enter either hiccup or latch-off as fault response as described in ? fault response register set_fault_response (d2h) ? on page 35 . page 59 table 6. pmbus? command summary (continued) command code command name access number of data bytes data format default setting descriptions refer to page
isl78229 45 fn8656.3 february 12, 2016 submit document feedback d2h set_fault_response read/write word 2 bit set by the hic/latch pin intersil defined register. each of bits[9:2] controls the respective type of 8 fault condition?s response as listed below. bit = 1 or 0 sets the fault protection response to be either hiccup or latch-off mode. bits [15:10]: not used bit [9]: pll_lock fault bit [8]: pllcomp_short fault bit [7]: vout_ov fault bit [6]: vout_uv fault bit [5]: oc2_ipeak fault bit [4]: oc_avg fault bit [3]: ot_ntc_fault fault bit [2]: vin_ov fault bit [1]: not used bit [0]: not used bit = 1 means hiccup mode bit = 0 means latch-off mode page 60 d3h vout_ov_fault_limit read/write byte 1 bit 06h intersil defined register. set the output overvoltage fault threshold for the output voltage measured at the fb pin. bits [7:3]: not used bits [2:0]: valid bits page 61 d4h vout_uv_fault_limit read/write byte 1 bit 01h intersil defined register. set the output undervoltage fault threshold for the output voltage measured at the fb pin. [7:3]: not used; [2:0] valid bits page 62 d5h cc_limit read/write byte 1 bit 07h intersil defined register. set the constant current control threshold for the boost input current measured at the imon pin. bits [7:3]: not used bits [2:0]: valid bits page 63 d6h oc_avg_fault_limit read/write byte 1 bit 07h intersil defined register. set the average overcurrent fault threshold for the boost input average current measured at the imon pin. bits [7:3]: not used bits [2:0]: valid bits page 64 table 6. pmbus? command summary (continued) command code command name access number of data bytes data format default setting descriptions refer to page
isl78229 46 fn8656.3 february 12, 2016 submit document feedback pmbus? command detail operation (01h) definition: sets to enable and disable the pwm regulating operation. only bits [7:6] are used for isl78229. if bits [7:6] are written to be 00b, the device turns off pwm regulation immediately. this comman d can also be monitored to read the operating state of the dev ice on bits [7:6]. the value read reflects the current state of the device. data length in bytes: 1 data format: bit field type: r/w protectable: yes default value: 80h (immediate off) units: n/a clear_faults (03h) definition: clears all fault bits that have been set in the fault_status register and releases the salert pin (if asserted) simultaneously . if a fault condition still exists when the bit is cleared, the fa ult bit will be set again immediately and the host notified by the salert pin. this command does not restart the isl78229 th at has latched off or been in hiccup mode for a fault condition, it only clears th e fault bits in the fault_status register and release the salert pin. this command is write only. there is no data byte for this command. data length in bytes: 0 byte data format: n/a type: send byte protectable: yes default value: n/a units: n/a command operation (01h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bits 7:6 bits 5:0 (not used) unit on or off 00 xxxxxx immediate off 10 xxxxxx on, normal operation
isl78229 47 fn8656.3 february 12, 2016 submit document feedback write_protect (10h) definition: this command is used to control writing to the isl78229. th e intent of this command is to provide protection against accidental changes. this command is not in tended to provide protection against delibe rate changes to a device?s configuration o r operation. all supported commands may have their para meters read, regardless of the write_protect settings. data length in bytes: 1 data format: bit field type: r/w byte protectable: yes default value: 00h units: n/a capability (19h) definition: this command provides the way for a host system to determine some key capabilities of the isl78229. data length in bytes: 1 data format: bit field type: read only protectable: n/a default value: b0h units: n/a command write_protect (10h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 value description 10000000 disable all writes except to the write_protect command 01000000 disable all writes except to th e write_protect and operation commands 00100000 disable all writes except to the write_protect, operat ion and vout_command commands 00000000 enable writes to all commands command capability (19h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 10110000 bit number description bit value meaning 7 packet error checking 1 packet error checking is supported 6:5 maximum bus speed 01 maximum supported bus speed is 400khz 4 smbalert# 1 the device does have a salert# pin and does support the smbus alert response protocol 3:0 reserved 0000 reserved
isl78229 48 fn8656.3 february 12, 2016 submit document feedback vout_command (21h) definition: this command sets or reports vref_dac which is the reference for the output voltage regulation as described in ? output voltage regulation loop ? on page 26 . the vout_command has two data bytes formatted as 16lu ( ? write/read the 16lu data as the 8-bit dac input ? on page 42 ). the bits [15:8] are not used. the bits [7:0] unsigned binary integer represents vref_dac value with 8mv lsb. use equation 22 on page 42 to convert the 16lu data?s 8-bit [7:0] unsigned binary integer to vref_dac, and use equation 2 on page 26 to convert vref_dac to v out . data length in bytes: 2 data format: 16lu type: r/w protectable: yes default value: 00c8h. with 00c8h = 200(decimal) and 8mv/lsb, meaning v refdac = 0.008 * 200 = 1.6v units: volts equation: v refdac = 0.008*vout_command as equation 22 on page 42 . then use equation 2 on page 26 to calculate v out . range : 0 to 2.04v example : vout_command = 00c8h = 200(decimal), use equation 22 on page 42 , vref_dac = 0.008 * 200 = 1.6v with r fb1 = 4.53k and r fb2 = 97.6k ( figure 4 on page 8 ), use equation 2 on page 26 to get v out = 36.07v command vout_command (21h) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 0000000011001000 bit number meaning 7:0 set/read the vref_dac voltage 15:8 not used
isl78229 49 fn8656.3 february 12, 2016 submit document feedback vout_transition_rate (27h) definition: when the isl78229 receives vout_command that causes the vref_dac and eventually output voltage to change, this command sets the rate in mv/ms at which the vref_dac changes, and correspondingly sets the rate at which the output voltage changes. this commanded rate of change does not apply wh en the unit is commanded to turn on or to turn off. the vout_transition_rate co mmand has two data bytes formatted in bit field as shown in the table below. bits [15:3] are not use d and bits [2:0] defines the transition rate of the vref_dac with default value of 0004h meaning 200mv/ms for vref _dac transition rate (per table below), and 8 options ranging from 12.5mv/ms to 1600mv/ms. according to equation 2 on page 26 , equation 24 below can be used to convert the v refdac transition rate (v refdactr ) to the v out transition rate (v outtr ), where r fb2 and r fb1 are resistor dividers from v out to fb as shown in figure 3 on page 7 . data length in bytes: 2 data format: bit field type : r/w protectable: yes default value: 0004h, which equals to 0000_0100b, meaning 200m v/ms as for transition rate of vref_dac units: mv/ms (referred for v refdac transition rate) equation: use equation 24 to convert the v refdac transition rate (v refdactr ) to the v out transition rate (v outtr ). range : 12.5mv/ms to 1600mv/ms for v refdac transition rate example : vout_transition_rate = 0003h = 0000_0000_0000_0011b sets the v refdac transition rate to be 100mv/ms. using equation 24 with r fb1 = 4.53k and r fb2 = 97.6k ( figure 4 on page 8 ), the v out transition rate (v outtr ) is calculated to be 2.25v/ms. command vout_transition_rate (27h) format bit field bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 0000000000000100 v outtr v refdactr 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 24) bits 15:3 (not used) bits 2:0 transition rate of vref_dac (mv/ms) not used 000 12.5 not used 001 25 not used 010 50 not used 011 100 not used 100 200 not used 101 400 not used 110 800 not used 111 1600
isl78229 50 fn8656.3 february 12, 2016 submit document feedback ot_ntc_fault_limit (4fh) definition: set/read the voltage threshold for the external over-temperature fault (ot_ntc_fault). as described in ? external temperature monitoring and protection (ntc pin) ? on page 38 , the ntc pin voltage represents the temperature of the board ( figure 71 on page 38 ). the isl78229 compares the ntc pin voltage v ntc to a voltage threshold which is set by this ot_ntc_fault_limit command to detect if ot_ntc_fault occurs. the ot_ntc_fault_limit command has tw o data bytes formatted as 16lu ( ? write/read the 16lu data to set ntc threshold ? on page 42 ). bits [15:10] are not used and bits [9:0] unsigned bi nary integer value represents the voltage threshold for v ntc with 2mv/lsb. the ot_ntc_fault_limit has default setting of 0096h meanin g 300mv threshold for v ntc . when v ntc is lower than 300mv (default), the ot_ntc_fault event is tr iggered. for detailed descriptions of this fault, refer to ? external over-temperature fault (ot_ntc_fault) ? on page 39 , table 3 on page 41 and the ? pmbus? command summary ? on page 43 to deactivate this fault and configure the fault response. to convert the voltage threshold to temper ature threshold, refer to the specific v ntc versus temperature characteristic curve (example figure 71 on page 38 ) for each specific application setup. data length in bytes: 2 data format: 16lu type : r/w protectable: yes default value: 0096h. with 0096h = 150(decimal) and 2mv/lsb, the ot_ntc_fault default threshold for v ntc is 150 * 2mv = 300mv. units: mv (referred for voltage threshold for v ntc with 2mv/lsb) equation: v ot_ntc_fault_limit = 0.002 * ot_ntc_fault_limit as equation 23 on page 42 , where ot_ntc_fault_limit is the 16lu data in this command, and v ot_ntc_fault_limit refers to the ot_ntc_fault threshold for v ntc range : 0 to 2.046v command ot_ntc_fault_limit (4fh) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 0000000010010110 bit number meaning 9:0 set/read the voltage threshold for v ntc as ot_ntc_fault fault detection with 2mv/lsb 15:10 not used
isl78229 51 fn8656.3 february 12, 2016 submit document feedback ot_ntc_warn_limit (51h) definition: set/read the voltage threshold for th e external over-temperature warning (ot_ntc_warn). as described in ? external temperature monitoring and protection (ntc pin) ? on page 38 , the ntc pin voltage represents the temperature of the board ( figure 71 on page 38 ). the isl78229 compares the ntc pin voltage v ntc to a voltage threshold which is set by this ot_ntc_warn_limit command to detect if ot_ntc_warn occurs. the ot_ntc_warn_limit command has two data bytes formatted as 16lu ( ? write/read the 16lu data to set ntc threshold ? on page 42 ). bits [15:10] are not used and bits [9:0] unsigned bi nary integer value represents the voltage threshold for v ntc with 2mv/lsb. the ot_ntc_warn_limit has default se tting of 00e1h meaning 450mv threshold for v ntc . when v ntc is lower than 450mv (default), the ot_ntc_warn warning event is triggered. for detailed descri ptions of this warning, refer to ? external over-temperature warning (ot_ntc_warn) ? on page 38 . to convert the voltage threshold for to temperature threshold, refer to the specific v ntc versus temperature characteristic curve (example figure 71 on page 38 ) for each specific application setup. data length in bytes: 2 data format: 16lu type : r/w protectable: yes default value: 00e1h. with 00e1h = 225(decimal) and 2mv/ lsb, the ot_ntc_warn default threshold for v ntc is 225 * 2mv = 450mv. units: mv (referred for voltage threshold for v ntc with 2mv/lsb) equation: v ot_ntc_warn_limit = 0.002 * ot_ntc_warn_limit as equation 23 on page 42 , where ot_ntc_warn_limit is the 16lu data in this command, and v ot_ntc_warn_limit refers to the ot_ntc_warn threshold for v ntc range : 0 to 2.046v (referred for voltage threshold for v ntc with 2mv/lsb) command ot_ntc_warn_limit (51h) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 0000000011100001 bit number meaning 9:0 set/read the voltage threshold for v ntc as ot_ntc_warn warning detection with 2mv/lsb 15:10 not used
isl78229 52 fn8656.3 february 12, 2016 submit document feedback read_vin (88h) definition: this command returns a voltage reading with va lue of vin/48 (vin pin voltage divided by 48). the read_vin command has two data bytes formatted as 16lu (refer to ? read the 16lu data to report the 10-bit adc input voltage ? on page 42 ), where the bits [15:10] are not used and bits [9:0] are used . the bits [9:0] unsigned binary integer value represents the vin/48 voltage value with 2mv/lsb. according to equation 21 on page 42 , equation 25 can be used to convert the 16lu data (bits [9:0] unsigned binary integer value, termed as co mmand) in this command to input voltage at the vin pin: data length in bytes: 2 data format: 16lu type: read only protectable: n/a default value: n/a units: volts (referred for vin/48 with 2mv/lsb, use equation 25 get v out ) equation: equation 25 range : 0 to 2.046v (referred for vin/48 with 2mv/lsb) example : read_vin = 007dh = 125(decimal), with 2mv/lsb and equation 25 , v in = 48 * 0.002 * 125 = 12v command read_vin (88h) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value n/a v in 48 0.002 command ?? = (eq. 25) bit number meaning 9:0 reports input voltage with value of vin/48 with 2mv/lsb. use equation 25 calculate the v in . 15:10 not used
isl78229 53 fn8656.3 february 12, 2016 submit document feedback read_vout (89h) definition: this command returns output voltage read ing with value of the fb pin voltage. the read_vin command has two data bytes formatted as 16lu (refer to ? read the 16lu data to report the 10-bit adc input voltage ? on page 42 ), where the bits [15:10] are not used and bits [9:0] are used. the bits [9:0] unsigned binary integer value represents the fb voltage value with 2mv/lsb. equation 26 can be used to convert the 16lu data (bits [9:0] unsigned binary integer value, termed as command) reported in this command to output voltage v fb : according to equation 2 on page 26 , equation 27 can be used to convert the 16lu data (b its [9:0] unsigned binary integer value, termed as command) reported in this command to output voltage v out , where r fb2 and r fb1 are resistor dividers from v out to fb as shown in figure 4 on page 8 : data length in bytes: 2 data format: 16lu type: read only protectable: n/a default value: n/a units: volts (referred for v fb with 2mv/lsb, use equation 27 get v out ) equation: equation 26 to calculate v fb and equation 27 to calculate v out range : 0 to 2.046v (referred for v fb with 2mv/lsb) example : read_vout = 0800h = 800(decimal). use equation 26 to get v fb = 0.002 * 800 = 1.6v. with r fb1 = 4.53k and r fb2 = 97.6k , use equation 27 to get v out = (1 + 97.6/4.53) * 0.002 * 800 = 36.072v. command read_vout (89h) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value n/a v fb 0.002 command ? = (eq. 26) v out 1 r fb2 r fb1 -------------- - + ?? ?? ?? 0.002 command ?? = (eq. 27) bit number meaning 9:0 reports the output voltage with value of the fb pin voltage with 2mv/lsb. use equation 26 to calculate v fb , and equation 27 to calculate the corresponding v out . 15:10 not used
isl78229 54 fn8656.3 february 12, 2016 submit document feedback read_iin (8ch) definition: this command returns input current information with value of the imon pin voltage (v imon ) which represents the 2-phase boost total input average current i in as described in ? average current sense for 2 phases - imon ? on page 32 . the read_iin command has two data by tes formatted as 16lu (refer to ? read the 16lu data to report the 10-bit adc input voltage ? on page 42 ), where the bits [15:10] are not used and bits [9:0] are used. the bits [9:0] unsigned binary integer value represents the imo n voltage value with 2mv/lsb. equation 28 can be used to convert the 16lu data (bits [9:0] unsigned binary integer value, termed as command) reported in this command to v imon : according to equations 13 and 14 , equation 29 can be used to convert the 16lu data (bits [9:0] unsigned binary integer value, termed as command) reported in this command to the total 2-phase current value as the boost input current i in , where r sen , r set and r imon are described in ? current sense ? on page 31 : data length in bytes: 2 data format: 16lu type: read only protectable: n/a default value: n/a units: volts (referred for v imon with 2mv/lsb. use equation 29 get i in , which has unit ?a?) equation: equation 28 to calculate v imon and equation 29 to calculate i in range : 0 to 2.046v (referred for v imon with 2mv/lsb) example : read_iin = 0800h = 800(decimal). use equation 28 to get v imon = 0.002 * 800 = 1.6v. with r sen = 1m , r set = 483.1 and r imon = 57.6k , use equation 29 to get i in = 41.65a. command read_iin (8ch) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value n/a v imon 0.002 command ? = (eq. 28) (eq. 29) i in command 0.002 ? r imon ----------------------------------------------------- 17 10 ? 6 C C ?? ?? 8r set ?? r sen --------------------------------------------------------------- ----------------------------------------------------- - =
isl78229 55 fn8656.3 february 12, 2016 submit document feedback read_temperature (8dh) definition: this command returns temperature informat ion with value of the ntc pin voltage (v ntc ), which represents the temperature of the board spot where the ntc resistor is placed (refer to ? external temperature monitori ng and protection (ntc pin) ? on page 38 ). the read_temperature command has two data bytes formatted as 16lu (refer to ? read the 16lu data to report the 10-bit adc input voltage ? on page 42 ), where the bits [15:10] are not used and bits [9:0] are used. the bits [9:0] unsigned binary integer value represents the vntc voltage value with 2mv/lsb. equation 30 can be used to convert the 16lu data (bits [9:0] unsigned binary integer value, termed as command) reported in this command to v ntc : to convert the v ntc voltage to temperature, refer to the specific v ntc versus temperature characteristic curve (example figure 71 on page 38 ) for each specific application setup. data length in bytes: 2 data format: 16lu type: read only protectable: n/a default value: n/a units: volts (referred for v ntc with 2mv/lsb) equation: equation 30 to calculate v ntc . use the specific v ntc versus temperature characteristic curve such as figure 71 on page 38 for the specific setup to convert ntc to temperature. range : 0 to 2.046v (referred for v ntc with 2mv/lsb) example : read_temperature = 00e1h = 225( decimal), with 2mv/lsb, use equation 30 to get v ntc = 225 * 2mv = 450mv. if v ntc versus temperature characteristic curve is figure 71 on page 38 , the temperature is around 1 02c reading from the figure. command read_temperature (8dh) format 16lu bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value n/a bit number meaning 9:0 reports the temperature information with valu e of the ntc pin voltage and with 2mv/lsb. use equation 30 to calculate the ntc pin voltage v ntc . use the specific v ntc versus temperature characteristic curve to convert vntc to temperature. 15:10 not used v ntc 0.002 command ? = (eq. 30)
isl78229 56 fn8656.3 february 12, 2016 submit document feedback pmbus_revision (98h) definition: the pmbus_revision command returns the revision of the p mbus? specification to which the device is compliant. data length in bytes : 1 data format: bit field type : read only protectable : n/a default value: 22h (part 1 revision 1.2, part 2 revision 1.2) units: n/a ic_device_id (adh) definition: reports device identification information. for isl78229, this command is normal re ad, and it returns the binary unsigned integer data with value correlates to the part number isl78229. data length in bytes: 2 data format: cus type: read only protectable: n/a default value: 8229h, which correlates to part number isl78229 units: n/a command pmbus_revision (98h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00100010 bits 7:4 part 1 revision bits 3:0 part 2 revision 0000 1.0 0000 1.0 0001 1.1 0001 1.1 00101.200101.2 command ic_device_id (adh) format cus bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function returns ic id as part number as ?8229h? default value 1000001000101001
isl78229 57 fn8656.3 february 12, 2016 submit document feedback ic_device_rev (aeh) definition: reports device revision information. for isl78229, this command is normal read, an d it returns the binary unsigned integer data with value correlates to the revision 0c01h. data length in bytes: 2 data format: cus type: read only protectable: no default value: 0c01h (initial release) units: n/a command ic_device_rev (aeh) format cus bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function returns ic revision information as ?0c01h? default value 0000110000000001
isl78229 58 fn8656.3 february 12, 2016 submit document feedback fault_status (d0h) definition: intersil defined register. this command reports if a specific fa ult condition has ever been triggered. each bit represents one specific fault condition (listed in table below). the meanings of bit value are defined as follows: ? bit = 1 means this fault occurred ? bit = 0 means this fault did not occur. bits [9:2] control total of 8 fault conditions . bits [15:10] and bits [1:0] are not used. for more descriptions about this comman d and related commands, also refer to ? fault flag register fault_status (d0h) and salert signal ? on page 34 and table 3 on page 41. data length in bytes: 2 data format: bit field type : r/w protectable: yes default value: 0000h units: n/a command fault_status (d0h) format bit field bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 0000000000000000 bit number fault name default value meaning 0 cml 0 communications warning (for unsupported command, pec error) 1 ot_ntc_warn 0 external over-temperature warn ing (ntc_pin <450mv as default, threshold programmable) 2 vin_ov 0 input overvoltage fault (vin_pin >58v) 3 ot_ntc_fault 0 external over-temperature fa ult (ntc_pin <300mv as default, threshold programmable) 4 oc_avg 0 input average overcurrent fault (imon_pin >2v as default, threshold programmable) 5 oc2_peak 0 per phase peak overcurrent fault (i senx >105a) 6 vout_uv 0 output undervoltage fault (fb_pi n <80% vref_dac as default, threshold programmable) 7 vout_ov 0 output overvoltage fault (fb_pin >120% vref_dac as default, threshold programmable) 8 pllcomp_short 0 pllcomp pin shorted to high potential voltages (pllcomp_pin >1.7v) 9 pll_lock 0 pll loop fault due to reaching minimum frequency (detect the minimum frequency of 37khz as typical) 15:10 not used 000000 not used
isl78229 59 fn8656.3 february 12, 2016 submit document feedback fault_mask (d1h) definition : intersil defined register. this command sets any specific fault pr otection to be masked (ignored) or not. each bit controls o ne specific fault condition (listed in table below) to be ignored or not. with any bit?s value setting to 1, the corresponding fau lt is masked (ignored), which means there is no fault protecting action taken by the device wh en that fault is triggered, and the isl78229 k eeps its normal pwm switching and operations. the meanings of bit value are defined as follows: ? bit = 1 means to ignore, no action taken as fault response. ? bit = 0 means to respond with protecting action, with part ente r either hiccup or latch-off as fault response as described in the ? fault response register set_ fault_response (d2h) ? on page 35 . bits [9:2] control total of 8 fault conditions . bits [15:10] and bits [1:0] are not used. at default, the vout_uv fault is ignored with bit [6] setting to 1 as default. also, refer to table 3 on page 41 for fault related registers summary. data length in bytes: 2 data format: bit field type : r/w protectable: yes default value: 0049h units: n/a command fault_mask (d1h) format bit field bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 0000000001001001 bit number fault name default value meaning 0n/a 1reserved 1n/a 0reserved 2 vin_ov 0 ignore input overvoltage fault (vin_pin >58v) 3 ot_ntc_fault 1 ignore external over-tempe rature fault (ntc_pin <300mv as default, threshold programmable) 4 oc_avg 0 ignore input average overcurrent fault (imon_pin >2v) 5 oc2_peak 0 ignore peak overcurrent fault (i senx >105a) 6 vout_uv 1 ignore output undervoltage fa ult (fb_pin <80% vref_dac as default, threshold programmable) 7 vout_ov 0 ignore output overvoltage fault (fb_pin >120% vref_dac as default, threshold programmable) 8 pllcomp_short 0 ignore pllcomp pin shorted to high potential voltages (pllcomp_pin >1.7v) 9 pll_lock 0 ignore pll loop fault due to reaching minimum frequency (detect the minimum frequency of 37khz as typical) 15:10 not used 000000 not used
isl78229 60 fn8656.3 february 12, 2016 submit document feedback set_fault_response (d2h) definition: set/read the fault protection response which is either hiccup or latch- off determined by the corresponding bit of set_fault_response register. the default value of the set_fault_response register is determined by the hic/latch pin configurations. ? when hic/latch pin is pulled high (vcc), ea ch of bits [9:0] is set to 1 as default ? when the hic/latch pin is pulled low (gnd), ea ch of bits [9:0] is set to 0 as default ? when bit = 1, the fault protec tion response is hiccup mode ? when bit = 0, the fault protection response is latch-off mode in hiccup mode, the device will stop switching when a fault cond ition is detected, and restart from soft-start after 500ms (typ ical). this operation will be repeated until fault conditions are completely removed. in latch-off mode, the device will stop switching when a fault co ndition is detected and pwm switching disabled even after faul t conditions are removed. in latch-off status, the internal ldo is active to maintain pvcc voltage, and pmbus? interface is acces sible for user to monitor the type of fault triggered or other parameters . by either toggling the en pin or cycling vcc/pvcc below the po r threshold will restart the system. for related descriptions, refer to ? fault response register set_fault_response (d2h) ? on page 35 , and table 3 on page 41 for some fault related registers summary. data length in bytes: 2 data format: bit field type : r/w protectable: yes default value: set by the hic/latch pin. 03ffh when hic/latch = vcc; 0000h when hic/latch = gnd. units: n/a command set_fault_respose (d2h) format bit field bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value (hic/latch = vcc) 0000001111111111 default value (hic/latch = gnd) 0000000000000000 bit number fault name default value meaning 0 not used set by the hic/latch pin not used 1 not used set by the hic/latch pin not used 2vin_ov set by the hic/latch pin input overvoltage fault (vin_pin >58v) protection response is hiccup when bit = 1, and latch-off when bit = 0 3ot_ntc_faultset by the hic/latch pin ntc over-temperature fault (ntc_pin <300mv as default, threshold programmable) protection response is hiccup when bit = 1, and latch-off when bit = 0 4oc_avg set by the hic/latch pin input average overcurrent fault (imon_pin >2v) protection response is hiccup when bit = 1, and latch-off when bit = 0 5oc2_peakset by the hic/latch pin peak overcurrent fault (i senx >105a) protection response is hiccup when bit = 1, and latch-off when bit = 0 6 vout_uv set by the hic/latch pin output undervoltage fault (fb_pin <80% vref_dac as default, threshold programmable) protection response is hiccup when bit = 1, and latch-off when bit = 0 7 vout_ov set by the hic/latch pin output overvoltage fault (fb_pin >120% vref_dac as default, threshold programmable) protection response is hiccup when bit = 1, and latch-off when bit = 0
isl78229 61 fn8656.3 february 12, 2016 submit document feedback vout_ov_fault_limit (d3h) definition: set/read the output overvoltage fault thre shold. the output overvoltage fault is generated by a comparator comparing the fb pin voltage with vout_ov threshold which has setting options based on percentage of the vref_dac reference voltage. this command set ov threshold with 8 options ranging from 105% to 1 25% of the reference voltage vref_dac. the default is set at 120% of vref_dac. equivalently the v out overvoltage threshold is set at the same percentage of v out target voltage (set by vref_dac) since the device uses the same fb voltage to regulate the output voltage with the same re sistor divider between v out and the fb pin. for example, at default, the v out overvoltage threshold is set at 120% of v out_target . according to equation 2 on page 26 , the default v out overvoltage threshold can be calculated using equation 31 . other threshold options can be calculated using equation 31 with 1.2 replaced with other percentage options. this fault detection is active at the beginning of soft-start (t 5 as shown in figure 67 on page 30 ). when ov fault occurs, the corresponding bit in the fault_status re gister is set to 1 and the salert pin is pulled low. the ov f ault protection response is by default active an d the fault response is either hiccup or latch-off determined by the corresponding b it of fault_response register of which default value is determined by the hic/latch pin. for related description, refer to ? output overvoltage fault ? on page 36 , table 3 on page 41 and the ? pmbus? command summary ? on page 43 to deactivate this fault and configure the fault response. data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 06h, which equals to 0000_0110b, meaning 120% of vref_dac units: % 8 pllcomp_short set by the hic/latch pin pllcomp_short fault (pllcomp_pin >1.7v) protection response is hiccup when bit = 1, and latch-off when bit = 0 9pll_lockset by the hic/latch pin pll loop fault (detect the minimum frequency of 37khz as typical) protection response is hiccup when bit = 1, and latch-off when bit = 0 15:10 not used 000000 not used command ovp_set (d3h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000110 bit number fault name default value meaning vout ovdefault 1.2 v ? refdac 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 31) bits 7:3 (not used) bits 2:0 percentage of vref_dac (%) not used 000 105 not used 001 107.5 not used 010 110 not used 011 112.5 not used 100 115 not used 101 117.5 not used 110 120 not used 111 125
isl78229 62 fn8656.3 february 12, 2016 submit document feedback vout_uv_fault_limit (d4h) definition: set/read the output undervolta ge fault threshold. the output undervoltage fault is generated by a comparator comparing the fb pin voltage with vout_uv threshold wh ich has setting options based on percentage of the vref_dac reference voltage. this command set uv threshold with 8 options rang ing from 75% to 95% of the reference voltage vref_dac. the default is set at 80% of vref_dac. equivalently the v out undervoltage threshold is set at the same percentage of v out target voltage (set by vref_dac) since the device uses the same fb voltage to regulate the output voltage with the same re sistor divider between v out and the fb pin. for example, at default, the v out undervoltage threshold is set at 80% of v out_target . according to equation 2 on page 26 , the default v out undervoltage threshold can be calculated using equation 32 . other threshold options can be calculated using equation 32 with 0.8 replaced with other percentage options. this fault is masked before soft-start completes (t 9 as shown in figure 67 on page 30 ) or when the device is disabled. during normal operation after soft-start co mpletes and part is enabled, when uv fault occurs, the corresponding bit in fault_st atus register is set to 1 and the salert pin is pulled low. but this uv fault protection response is masked by the fault_mask regist er by default. for related descriptions and commands? details, refer to ? output undervoltage fault ? on page 35 , table 3 on page 41 and ? pmbus? command summary ? on page 43. data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 01h, which equals to 0000_0001b, meaning 80% of vref_dac units: v (referred for the vout_uv threshold v out_uv calculated by equation 32 ) command uvp_set (d4h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000001 vout uv command v ? refdac 1 r fb2 r fb1 -------------- - + ?? ?? ?? ? = (eq. 32) bits 7:3 (not used) bits 2:0 percentage of vref_dac (%) not used 000 75 not used 001 80 not used 010 82.5 not used 011 85 not used 100 87.5 not used 101 90 not used 110 92.5 not used 111 95
isl78229 63 fn8656.3 february 12, 2016 submit document feedback cc_limit (d5h) definition: set/read the reference voltage v ref_cc for constant current control loop described in ? constant current control (cc) ? on page 37 . at overloading condition wh en constant current control loop is working, the v imon is controlled to be equal to the 1.6v reference (v ref_cc ) by default. since v imon represents the boost tota l input average current i in as described in ? average current sense for 2 phases - imon ? on page 32 , the i in is controlled to be constant by the cc loop. this command can set cc reference to 8 options ranging from 1.25v to 1.6v with default setting of 1.6v. from equations 13 and 14 , equation 33 can be derived to convert the 8 cc reference options in below table (as v imon in the equation) to the actual total boost input current thresholds for cc, where command in the equation is the voltage options (cc_limit refer ence voltage) in the command table shown in following. for related description, refer to ? constant current control (cc) ? on page 37 . data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 07h, which equals to 0000_0111b, meaning v ref_cc = 1.6v (per table ) for v imon to follow at cc control. units: v (referred for the reference voltage v ref_cc for v imon to follow); a (referred for the boost average input current converted by equation 33 ) command cc_limit (d5h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000111 i in command r imon --------------------------------- - 17 10 ? 6 C C ?? ?? r set r sen --------------- - 8 ?? = (eq. 33) bits 7:3 (not used) bits 2:0 cc reference voltage v ref_cc (v) not used 000 1.25 not used 001 1.3 not used 010 1.35 not used 011 1.4 not used 100 1.45 not used 101 1.5 not used 110 1.55 not used 111 1.6
isl78229 64 fn8656.3 february 12, 2016 submit document feedback oc_avg_fault_limit (d6h) definition: set/read the input average overcurrent fa ult threshold. the input average overcurre nt fault is generated by a comparator comparing the imon pin voltage with 2v thre shold as default. this command sets the oc _avg fault threshold with 8 options rangin g from 1v to 2v. the default is set at 07h meaning 2v for v imon . use equation 33 to convert the oc_avg fault thresholds in following table to the actual total boost inpu t average current protection thresholds. this fault detection is active at the beginning of soft-start (t 5 as shown in figure 67 on page 30 ). when an oc_avg fault occurs, the corresponding bit in the fault_st atus register is set to 1 and the salert pin is pulled low. t he oc_avg fault protection is by default acti ve and the fault response is either hiccup or latch-off determined by the correspondi ng bit of fault_response register of which default value is determined by the hic/latch pin. for related description, refer to ? average overcurrent fault (oc_avg) ? on page 38 , table 3 on page 41 and the related commands in ? pmbus? command summary ? on page 43 to deactivate this fault and configure the fault response. data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 07h, which equals to 0000_0111b, meanin g 2v threshold for the imon pin voltage (v imon ) to detect oc_avg fault. units: v command oc_avg_fault_limit (d6h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000111 bits 7:3 (not used) bits 2:0 oc_avg threshold for v imon (v) not used 000 1 not used 001 1.15 not used 010 1.25 not used 011 1.4 not used 100 1.55 not used 101 1.7 not used 110 1.85 not used 111 2
isl78229 65 fn8656.3 february 12, 2016 submit document feedback application information there are several ways to define the external components and parameters of boost regulators. this section shows one example of how to decide the parameters of the external components based on the typical application schematics as shown in figure 4 on page 8 . in the actual application, the parameters may need to be adjusted and additional components may be needed for the specific applications regarding noise, physical sizes, thermal, testing and/or other requirements. output voltage setting the output voltage (v out ) of the regulator can be programmed by an external resistor divider connecting from v out to fb and fb to gnd as shown in figure 4 on page 8 . use equation 2 on page 26 to calculate the desired v out , where v ref can be either vref_dac or vref_trk, whichever is lower. vref_dac default is 1.6v and can be programmed to a value between 0v to 2.04v via pmbus? command ? vout_command (21h) ? on page 48 . in the actual application, the resistor value should be decided by considering the quiescent current requirement and loop response. typically, between 4.7k to 20k will be used for the r fb1 . switching frequency switching frequency is determined by requirements of transient response time, solution size, emc/emi, power dissipation and efficiency, ripple noise level, input and output voltage range. higher frequency may improve the transient response and help to reduce the solution size. however, this may increase the switching losses and emc/emi concerns. thus, a balance of these parameters are needed when deciding the switching frequency. once the switching frequency f sw is decided, the frequency setting resistor (r fsync ) can be determined by equation 6 on page 29 . input inductor selection while the boost converter is operat ing in steady state continuous conduction mode (ccm), the output voltage is determined by equation 1 on page 25 . with the required input and output voltage, duty cycle d can be calculated by equation 34 : where d is the on-duty of the boost low-side power transistor. under this ccm condition, the inductor peak-to-peak ripple current of each phase can be calculated as equation 35 : where t is the switching cycle 1/f sw and l is each phase inductor's inductance. from the previous equations, the inductor value is determined by equation 36 : use equation 36 to calculate l, where values of v in , v out and i lpp are based on the considerations described in the following: ? one method is to select th e minimum input voltage and the maximum output voltage under long term operation as the conditions to select the inductor . in this case, the inductor dc current is the largest. ? the general rule to select inductor is to have its ripple current i l(p-p) around 30% to 50% of maximum dc current. the individual maximum dc inductor current for the 2-phase boost converter can be calculated by equation 37 , where p outmax is the maximum dc output power, eff is the estimated efficiency: using equation 36 with the two conditions listed above, a reasonable starting point for the minimum inductor value can be estimated from equation 38 , where k is typically selected as 30%. increasing the value of the inductor reduces the ripple current and therefore the ripple voltage. however, the large inductance value may reduce the converter?s response time to a load transient. also, this reduces th e ramp signal and may cause a noise sensitivity issue. the peak current at maximum load condition must be lower than the saturation current rating of the inductor with enough margin. in the actual design, the largest peak current may be observed at some transient conditions like the start-up or heavy load transient. therefore, the inductor?s size needs to be determined with the consideration of these conditions. to avoid exceeding the inductor?s saturation rating, oc1 peak current limiting (refer to ? peak current cycle-by-cycle limiting (oc1) ? on page 36 ) should be selected below the inductor?s saturation current rating. output capacitor to filter the inductor current ripples and to have sufficient transient response, output capacitors are required. a combination of electrolytic and ceramic capacitors are normally used. the ceramic capacitors are used to filter the high frequency spikes of the main switching devices. in layout, these output ceramic capacitors must be placed as close as possible to the main switching devices to maintain the smallest switching loop in layout. to maintain capacitance over the biased voltage and temperature range, good quality capacitors such as x7r or x5r are recommended. the electrolytic capacitors are normally used to handle the load transient and output ripples. the boost output ripples are mainly dominated by the load current and output capacitance volume. for boost converter, the maximum output voltage ripple can be estimated using equation 39 , where i outmax is the load current at output, c is the total capacitance at output, and d min is the minimum duty cycle at vin max and vout min . (eq. 34) d1 v in v out --------------- - C = i l(p-p) dt vin l ---------- ?? = (eq. 35) l1 v in v out --------------- - C ?? ?? ?? v in i l(p-p) f sw ? ------------------------------- - ? = (eq. 36) i lmax p outmax v inmin eff 2 ?? ------------------------------------------- - = (eq. 37) l min 1 v inmin v outmax -------------------------- - C ?? ?? ?? v inmin 2 eff 2 ?? p outmax kf sw ?? -------------------------------------------------- - ? = (eq. 38) v outripple i outmax 1d min C ?? ? c2f sw ?? ---------------------------------------------------------- = (eq. 39)
isl78229 66 fn8656.3 february 12, 2016 submit document feedback for a 2-phase boost converter, the rms current going through the output current can be calculated by equation 39 for d > 0.5, where i l is per phase inductor dc current. for d < 0.5, time domain simulation is recommended to get the accurate calculation of the input capacitor rms current. it is recommended to use multip le capacitors in parallel to handle this output rms current. input capacitor depending upon the system input power rail conditions, the aluminum electrolytic type capacitors are normally used to provide a stable input voltage. the input capacitor should be able to handle the rms current from the switching power devices. refer to equation 5 and figure 62 on page 28 to estimate the rms current the input capacitors need to handle. ceramic capacitors must be placed near the vin and pgnd pin of the ic. multiple ceramic capacitors including 1f and 0.1f are recommended. place these capacitors as close as possible to the ic. power mosfet the external mosfets driven by the isl78229 controller need to be carefully selected to optimize the design of the synchronous boost regulator. the mosfet's bv dss rating needs to have enough voltage margin against the maximum bo ost output voltage plus the phase node voltage transient during switching. as the ug and lg gate drivers are 5v output, the mosfet v gs need to be in this range. the mosfet should have low total gate charge (q g ), low on-resistance (r ds(on) ) at vgs = 4.5v and small gate resistance (r g <1.5 is recommended). it is recommended that the minimum v gs threshold is higher than 1.2v but not exceeding 2.5v, in order to prevent false turn-on by noise spikes due to high dv/dt during phase node sw itching and maintain low r ds(on) under limitation of maximum gate drive voltage, which is 5.2v (typical) for low-side mosfet and 4.5v (typical) due to diode drop of boot diode for high-side mosfet. bootstrap capacitor the power required for high-side mosfet drive is provided by the boot capacitor connected between boot and ph pins. the bootstrap capacitor can be chosen using equation 41 : where q gate is the total gate charge of the high-side mosfet and dv boot is the maximum droop voltage across the bootstrap capacitor while turning on the high-side mosfet. though the maximum charging voltage across the bootstrap capacitor is pvcc minus the bootstrap diode drop (~4.5v), large excursions below gnd by ph node requires at least 10v rating for this ceramic capacitor. to keep enough capacitance over the biased voltage and temperature ra nge, a good quality capacitor such as x7r or x5r is recommended. resistor on bootstrap circuit in the actual application, someti mes a large ringing noise at the ph node and the boot node are observed. this noise is caused by high dv/dt phase node switching, parasitic ph node capacitance due to pcb routing an d the parasitic inductance. to reduce this noise, a resistor can be added between the boot pin and the bootstrap capacitor. a large resistor value will reduce the ringing noise at ph node but limi ts the charging of the bootstrap capacitor during the low-side mo sfet on-time, especially when the controller is operating at ve ry low duty cycle. also large resistance causes voltage dip at boot each time the high-side driver turns on the high-side mosfet. make sure this voltage dip will not trigger the high-side boot to ph uvlo threshold 3v (typical), especially when a mosfet with large q g is used. loop compensation design the isl78229 uses constant frequency peak current mode control architecture with a gm amp as the error amplifier. figures 74 and 75 show the conceptual schematics and control block diagram, respectively. i coutrms i l 1d C ?? 2d 1 C ? ?? ? ? = (eq. 40) c boot q gate dv boot ----------------------- - ? (eq. 41) figure 74. conceptual block diagram of peak current mode controlled boost regulator - + gm v ref vo r cp c cp2 fb comp r fb2 r fb1 r 1 c 1 c cp1 r oea - + - + gm slope v in r sen v out r l r esr c out l gvcvo(s) he2(s) he1(s) vc vfb
isl78229 67 fn8656.3 february 12, 2016 submit document feedback transfer function from v c to v out transfer function from error amplifier output v c to output voltage v out g vcvo (s) can be expressed as equation 42 . the expressions of the pole s and zeros are listed below: where, ? n is the number of phases, r esr is the output capacitor?s equivalent series resistance (esr) of the total capacitors, r load is the load resistance, l eq is the equivalent inductance for multiphase boost with n number of phases, l is the inductance on each phase. ?k isen is the current sense gain as shown in equation 43 , where r senx and r setx are per phase current sense resistor and setting resistors described in ? current sense for individual phase - i senx ? on page 32 . ? se/sn is gain of the selected compensating slope over the sensed inductor current up-ram p. it can be calculated in equation 44 , where k slope is the gain of selected compensating slope over the sensed i l down slope (refer to equation 15 on page 33 ). equation 42 shows that the system is mainly a single order system plus a right half zero (rhz), which commonly exists for boost converter. the main pole pps is determined by load and output capacitance and the esr zero esr is the same as buck converter. since the rhz changes with load, typically the boost converter crossover frequency is set 1/5 to 1/3 of the rhz frequency. the double pole n is at half of the f sw and has minimum effects at crossover frequency for most of the cases when the crossover frequency is fairly low. compensator design generally simple type-2 compensator can be used to stabilize the system. in the actual application, however, an extra phase margin will be provided by a type-3 compensator. the transfer function at the erro r amplifier and its compensation network will be expressed as equation 45 . figure 75. conceptual control block diagram *yfyrv &xuuhqwprghfrqwuro 3rzhu6wdjh +hv (uuru$ps c 9r c 9ie c 9f .ie 9uhi 9ie g vcvo s ?? k dc 1 s ? esr ----------- - + ?? ?? 1 s ? rhz --------------- C ?? ?? ? 1 s ? p1 ---------- + ?? ?? 1 s q p ? n ? ------------------- s ? n ------ - ?? ?? 2 ++ ?? ?? ? --------------------------------------------------------------- ------------------------ - ? = (eq. 42) k dc r load 1d C ?? ? k isen ------------------------------------------ - = ? rhz r load 1d C ?? 2 ? l eq --------------------------------------------- - = ? esr 1 c out r esr ? --------------------------------- = ? pps 2 c out r load ? ---------------------------------------- - = q p 1 ? 1d C ?? s e s n ------ - ? 0.5 d ++ ? --------------------------------------------------------------- ----- - = ? n 2 f sw -------- = l eq l n --- - = k isen r senx 6500 ? r setx ------------------------------------ - = (eq. 43) s e s n ------ - k slope v out v in --------------- - 1 C ?? ?? ?? ? = (eq. 44) figure 76. type-3 compensator - + gm vref vo rcp ccp2 fb vc rfb2 rfb1 r1 c1 ccp1 roea he2(s) he1(s) comp h e2 s ?? v c v fb ---------- - g m z comp = ? == (eq. 45) g m 1sr cp c cp 1 + ?? r oea 1sr cp c cp1 r o e a c cp1 c cp2 + ?? + ?? c c p 2 c cp1 r cp r o ea s 2 ++ --------------------------------------------------------------- --------------------------------------------------------------- --------------------------------------------------------------- -------------
isl78229 68 fn8656.3 february 12, 2016 submit document feedback if r oea >>r cp , c cp1 >>c cp2 , and r oea = infinite, the equation can be simplified as shown in equation 46 : where: if type-3 compensation is needed, the transfer function at the feedback resistor network is: where: the total transfer function with compensation network and gain stage will be expressed: use f = /2 to convert the pole and zero expressions to frequency domain, and from equations 42 , 47 and 48 , select the compensator?s pole and zero locations. in general, as described earlier, a type-2 compensation is enough. typically the crossover freq uency is set 1/5 to 1/3 of the rhz frequency. for the compensator as general rule, set p2 /2 at very low end frequency; set z2 /2 at 1/5 of the crossover frequency; set p3 /2 at the esr zero or the rhz frequency rhz /2 , whichever is lower. vcc input filter to provide a quiet power rail to the internal analog circuitry, it is recommended to place an rc filter between pvcc and vcc. a 10 resistor between pvcc and vcc and at least 1f ceramic capacitor from vcc to gnd are recommended. current sense circuit to set the current sense resistor , the voltage across the current sense resistor should be limited to within 0.3v. in a typical application, it is recommended to set the voltage across the current sense resistor between 30mv to 100mv for the typical load current condition. layout considerations for dc/dc converter design, the pc b layout is very important to ensure the desired performance. 1. place input ceramic capacitors as close as possible to the ic's vin and pgnd/sgnd pins. 2. place the output ceramic capacitors as close as possible to the power mosfet. keep this loop (output ceramic capacitor and mosfets for each phase) as small as possible to reduce voltage spikes induced by the trace parasitic inductances when mosfets switching on and off. 3. place the output aluminum capacitors close to power mosfets too. 4. keep the phase node copper area small but large enough to handle the load current. 5. place the input aluminum and some ceramic capacitors close to the input inductors and power mosfets. 6. place multiple vias under the thermal pad of the ic. the thermal pad should be connected to the ground copper plane with as large an area as possible in multiple layers to effectively reduce the thermal impedance. figure 77 shows the layout example for vias in the ic bottom pad. 7. place the 10f decoupling ceramic capacitor at the pvcc pin and as close as possible to the ic. put multiple vias close to the ground pad of this capacitor. 8. place the 1f decoupling ceramic capacitor at the vcc pin and as close as possible to the ic. put multiple vias close to the ground pad of this capacitor. 9. keep the bootstrap capacitor as close as possible to the ic. 10. keep the driver traces as short as possible and with relatively large width (25mil to 40 mil is recommended), and avoid using vias or a minimal number of vias in the driver path to achieve the lowest impedance. 11. place the current sense setting resistors and the filter capacitor (shown as r setxb , r biasxb and c isenx in figure 69 on page 32 ) as close as possible to the ic. keep each pair of the traces close to each other to avoid undesired switching noise injections. 12. the current sensing traces must be laid out very carefully since they carry tiny signal s with only tens of mv. for the current sensing traces close to the power sense resistor (r senx ), the layout pattern shown in figure 78 is recommended. h e2 s ?? g m 1sr cp c cp1 ?? + sc cp1 1sr cp c cp2 ?? + ?? ?? --------------------------------------------------------------- ------------------ - ? ? 1 s ------ - 1 s ? z2 --------- - + 1 s ? p2 ---------- + -------------------- ? == (eq. 46) ? p2 g m c cp1 --------------- = ? z2 1 r cp c cp1 ? ------------------------------- - = ? p3 1 r cp c cp2 ? ------------------------------- - = h e1 s ?? r fb1 r fb1 r fb2 + ----------------------------------- - 1 s ? z1 --------- - + 1 s ? p1 ---------- + -------------------- ? = (eq. 47) ? z1 1 c 1 r fb2 r 1 + ?? ? --------------------------------------------- = ? p1 1 c 1 r fb2 r fb1 ? r fb2 r 1 ? r fb1 r 1 ? ++ r fb2 r fb1 + --------------------------------------------------------------- ------------------------------------- - ? --------------------------------------------------------------- ------------------------------------------------- - = g open s ?? g vcvo s ?? h e1 s ?? h e2 s ?? ?? = (eq. 48) figure 77. recommended layout pattern for vias in the ic bottom pad
isl78229 69 fn8656.3 february 12, 2016 submit document feedback assuming the r senx is placed in the top layer (red), route one current sense connection fr om the middle of one r senx pad in the top layer under the resistor (red trace). for the other current sensing trace, from the middle of the other pad on r senx in top layer, after a short distance, via down to the second layer and route this trace right under the top layer current sense trace. 13. keep the current sensing traces far from the noisy traces like gate driving traces (lgx, ugx and phx), phase nodes in power stage, bootx signals, output sw itching pulse currents, driving bias traces and input inductor ripple current signals, etc. figure 78. recommended la yout pattern for current sense traces regulator
isl78229 70 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8656.3 february 12, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change february 12, 2016 fn8656.3 -table 4 on page 41 updated d2h descriptions -pmbus command summary table 6 on page 43, simplified d2h descriptions. -set_fault_response (d2h) on page 60 changes as follow: changed 0000h to 03ffh, 00ffh to 0000h. changed from "not used" to "set by the hic/latch pin" (2 places) changed from "all the bits are set to 1 as default" to "each of bits[9:0] is set to 1 as default" changed from "all the bits are set to 0 as default" to "each of bits[9:0] is set to 0 as default" february 4, 2016 fn8656.2 changed in figure 16 on page 17 labe l ?il1? to il2? and in title ?phase 1? to ?phase 2?. january 4, 2016 fn8656.1 updated 2nd and 3rd paragraph in section ?external over-temperature fault (ot_ntc_fault)? on page 39 for clarity and changed in 4th paragraph ?450mv? to ?300mv?. changed in "ic_device_rev (aeh)", "0b01h" and ?010 ch? to "0c01h" and changed default value in table starting with the 6th number from ?...011...? to ?...100...? on page 43 and page 57. changed default value for ?fault_mask from "0043h" to "0049h on page 41 and page 59 updated the table bit value: from: 0000-0000-0100-0011; to: 0000-0000-0100-1001 updated d1h default value column in table 4 on page 41. updated expression qp and equation 44 on page 67 removed text after equation 44 on page 67 and before paragraph that begins with ?equation 42?. november 23, 2015 fn8656.0 initial release
isl78229 71 fn8656.3 february 12, 2016 submit document feedback package outline drawing l40.6x6c 40 lead quad flat no-lead plastic pack age (punch qfn with wettable flank) rev 1, 1/14 bottom view side view typical recommended land pattern top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the pla ted terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: 0.60 dia. 2x a 2x 0.10 b c 0.85 0.05 n n 5 3 2 0.50 1 0.05 b c 0.10 2x c 0.10 0.10 2x b 0.01 0.04 a c 6 c c a 0.20 0.65 0.05 pin#1 id r0.20 0.10 c 3 2 1 (0.35) 4.5 0.25 0.05 0.05 0.10 m m b a c c 4.5 0.45 5.75 6.00 5.75 6.00 0.10 a c m b 0.10 a c m b 0.15 0.10 (0.35) 0.40 0.10 seating plane 0.01 0.04 0.10 0.05 0.15 0.05 0.25 0.05 4 see detail "a" 4x 0.42 0.18 4x 0.42 0.18 0.25 0.05 0.01 0.04 40x (0.60) 40x (0.25) 36x (0.50) (4.50) sq (5.80) sq ? 12 max section c-c scale: none detail a scale: none reference document: jedec mo220 6. cc

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